DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 21, 22 and 26-28 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected sub-subspecies 1 and 3, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/2/2026.
Applicant’s election without traverse of sub-subspecies 2 drawn to claims 1-20, 23-25 and 29-31 in the reply filed on 2/2/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14, 16-18, 20, 23 and 29-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Pub. No. 2021/0057659 A1 to Sun et al.
As to claim 1, Sun discloses a display apparatus comprising:
a substrate comprising a first island portion and a second island portion spaced apart from each other, and a first bridge portion connecting the first island portion to the second island portion (Fig. 4a, 4b and 4f, paragraphs 0046-0057, where substrate (100) comprises first island-shaped circuit block (201) and second island-shaped circuit block (202) and they are connected via connection wire (220));
a gate driving circuit disposed on the first island portion (Fig. 4a, paragraphs 0051-0054, where a gate driving circuit is disposed on first island-shaped circuit block (201));
a plurality of first input lines disposed on the second island portion (Fig. 4g, paragraph 0058, where connection bridges (41-45) are input lines); and
a connection line connected to some of the plurality of first input lines (Fig. 4f, paragraph 0057, where connection wire (228) is the connection line),
wherein the connection line is arranged to extend from the second island portion to the first island portion through the first bridge portion (Fig. 4f, paragraph 0057, where connection wire (228) extends from second island (202) to first island (201) via connection wire (220)).
As to claim 2, Sun discloses the display apparatus, wherein the first island portion and the second island portion are arranged alternately in a first direction (Fig. 4a, paragraph 0051, where first island portion (201) and second island portion (202) alternate).
As to claim 3, Sun discloses the display apparatus, wherein the connection line comprises:
a first portion extending in the first direction on the first island portion; and
a second portion branching from the first portion and extending in a second direction intersecting the first direction (Fig. 4f, paragraph 0057, where connection wire (220) is S shaped and therefore has two extending portions).
As to claim 4, Sun discloses the display apparatus,
wherein the gate driving circuit comprises a plurality of stages (Fig. 5, paragraph 0059, where GGOA circuit block (2012) has two stages),
at least one stage of the plurality of stages is disposed on the first island portion, and the second portion is connected to the at least one stage (Fig. 4A and 5, paragraph 0059, where GGOA circuit block (2012) is disposed on first island portion (201)).
As to claim 5, Sun discloses the display apparatus, wherein
the plurality of first input lines comprise at least one of a gate high voltage line or a gate low voltage line, and
the connection line comprises at least one of: a high voltage connection line connected to the gate high voltage line; or a low voltage connection line connected to the gate low voltage line (Fig. 4a, paragraph 0053, where second island-shaped circuit block (202) provides first and second supply voltages (VSS, VDD)).
As to claim 6, Sun discloses the display apparatus, wherein the high voltage connection line comprises a portion having a 'T' shape in a plan view (Fig. 4g, paragraph 0057, where voltage connection line (VSS) is T shaped).
As to claim 7, Sun discloses the display apparatus, wherein the high voltage connection line comprises:
a first portion extending in a first direction from the first bridge portion toward a center of the first island portion; and
a second portion branching from the first portion and extending in a second direction intersecting the first direction (Fig. 4g, paragraph 0057, where a first portion extends to first island portion (201) and second portion extends in a second direction).
As to claim 8, Sun discloses the display apparatus, wherein the first portion of the high voltage connection line and the second portion of the high voltage connection line are disposed in a same layer and are formed integrally with each other (Fig. 4g, paragraph 0057, where the first and second portions of voltage line (VSS) are on the same layer as they are connected with each other).
As to claim 9, Sun discloses the display apparatus, wherein the low voltage connection line has a portion having a loop shape having one side open in a plan view (Fig. 4g, paragraphs 0057-0058, where voltage line (VDD, 45) has a loop shape).
As to claim 10, Sun discloses the display apparatus, wherein the low voltage connection line comprises:
a first portion extending in a first direction from the first bridge portion toward a center of the first island portion (Fig. 4g, paragraphs 0057-0058, where low voltage line (VDD, 45) extends through the center of the island portion); and
a second portion branching from the first portion, surrounding at least a portion of the gate driving circuit in the plan view, and having a quadrangular shape with one side open (Fig. 4g, paragraphs 0057-0058, where low voltage line (VDD, 45) branches as connection wire (227) with several angles).
As to claim 11, Sun discloses the display apparatus, wherein the high voltage connection line extends through the open side of the second portion (Fig. 4g, paragraphs 0057-0058, high voltage line (VSS, 42)).
As to claim 12, Sun discloses the display apparatus, wherein the first portion of the low voltage connection line and the second portion of the low voltage connection line are formed integrally with each other (Fig. 4g, paragraphs 0057-0058, where low voltage line (VSS, 42) has two portions connected together).
As to claim 13, Sun discloses the display apparatus, wherein the low voltage connection line comprises:
a first portion extending in a first direction from the first bridge portion disposed on one side surface of the first island portion toward an opposite side surface of the first island portion; and
a second portion branching from the first portion and extending in a second direction intersecting the first direction (Fig. 4f, paragraph 0057, where connection wire (228) extends in a first direction from one side of first island portion (201) to an opposite side surface of another first island portion (201)).
As to claim 14, Sun discloses the display apparatus, wherein the first portion of the low voltage connection line comprises a portion having a diagonal shape extending in a diagonal direction between the first direction and the second direction (Fig. 4f, paragraph 0057, where connection wire (228) has a diagonal portion).
As to claim 16, Sun discloses the display apparatus, further comprising a plurality of second input lines arranged on the first island portion, wherein the plurality of second input lines comprise at least one of a clock line, a carry line, or a reset signal line (Fig. 5, paragraph 0059, where (ECK, GCK) are clock signals).
As to claim 17, Sun discloses the display apparatus, further comprising:
a main island portion disposed in a display area (Fig. 5, paragraph 0059, where display block (31) is the display area);
a pixel driving circuit portion disposed on the main island portion (Fig. 5, paragraph 0059, where EGOA and GGOA circuits (2011, 2012) are pixel drivers); and
a light-emitting element disposed on the main island portion and connected to the pixel driving circuit portion (Fig. 5, paragraph 0059, where display block (31) has light-emitting elements),
wherein the pixel driving circuit portion and the light-emitting element are connected to each other through at least one of: a first connection piece disposed on the pixel driving circuit portion; or a second connection piece disposed on the first connection piece (Fig. 5, paragraph 0059, where EGOA (2011), GGOA (2012) and display block (31) are connected together).
As to claim 18, Sun discloses the display apparatus, wherein a partial region of the clock line disposed on the first island portion has a double wiring structure including a lower clock line and an upper clock line disposed on the lower clock line (Fig. 5, paragraph 0059, where clock (GCK) has an upper and lower line).
As to claim 20, Sun discloses the display apparatus, wherein each of the first island portion and the second island portion is provided in plurality,
wherein the display apparatus further comprises a second bridge portion connecting first island portions arranged adjacent to each other among the plurality of first island portions or connecting second island portions arranged adjacent to each other among the plurality of second island portions (Fig. 4a, paragraph 0053, where bridges (32, 33) connect first and second island portions (201, 202)),
wherein each of the plurality of first input lines and the plurality of second input lines extends through the second bridge portion (Fig. 5, paragraph 0059, where the input lines extend as shown in the figure).
As to claim 23, Sun discloses the display apparatus, wherein each of the plurality of first input lines and the plurality of second input lines comprises a lower input line and an upper input line disposed on the lower input line and has a dual wiring structure on the second bridge portion (Fig. 5, paragraph 0059, where the input lines are a plurality of lower and upper input lines as shown in the figure).
As to claim 29, Sun discloses the display apparatus, wherein the gate driving circuit comprises at least one of an emission control driving circuit, a bypass driving circuit, an initialization driving circuit, or a data writing driving circuit (Fig. 4a, paragraph 0054, where light emitting signal driving circuit (EGOA, EM-GOA) is the emission control driving circuit).
As to claim 30, Sun discloses the display apparatus, wherein the first bridge portion is disposed on a center of a side surface of each of the first island portion and the second island portion (Fig. 4f, paragraph 0057, where connection wire (228) is disposed on the center).
As to claim 31, Sun discloses the display apparatus, wherein the first bridge portion has a serpentine shape (Fig. 4f, paragraph 0057, where connection wire (228) is serpentine shape).
Allowable Subject Matter
Claims 15, 19, 24 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the first portion of the low voltage connection line and the second portion of the low voltage connection line are arranged in different layers from each other and are electrically connected to each other through a contact hole”, in combination with the other limitations set forth in claim 15.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the lower clock line is disposed in a same layer as a layer in which at least one of a source electrode or a drain electrode of the pixel driving circuit portion is disposed, and the upper clock line is disposed in a same layer as a layer in which the first connection piece is disposed”, in combination with the other limitations set forth in claim 19.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the lower input line is disposed in a same layer as a layer in which at least one of a source electrode or a drain electrode of the pixel driving circuit portion is disposed, and the upper input line is disposed in a same layer as a layer in which the first connection piece is disposed”, in combination with the other limitations set forth in claim 24.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record alone, or in combination, fail to teach, disclose, or render obvious, “wherein the lower input line and the upper input line are electrically connected to each other through a contact hole, and the contact hole is disposed on the first island portion or the second island portion”, in combination with the other limitations set forth in claim 25.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEETA YODICHKAS whose telephone number is (571)272-9773. The examiner can normally be reached Monday-Friday 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ANEETA YODICHKAS
Primary Examiner
Art Unit 2627
/ANEETA YODICHKAS/Primary Examiner, Art Unit 2627
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