DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 11 16-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin 9207922 herein Jin in view of Jayasena 20210182262 herein Jayasena.
Per claim 1, Jin discloses: a processing pipeline comprising a first processing stage to update and record a first number of access counts targeting a logical grouping of memory locations (col. 14; profile an access count of a block in a control flow of a program code; determine that the block is an important block in response to an edge count of an edge entering the block being greater than or equal to a predetermined value, the edge count being included in the access count; schedule the important block in the pipeline based on the access count to prevent a register writeback conflict, schedule an operation absent executing writeback in a cycle in which the register writeback conflict is expected in the important block;) and a second processing stage to continuously sort the first number of access counts and their associated address tags corresponding to the logical grouping of memory locations, (col. 14; form a superblock from the block based on the access count; sort the block and the superblock according to a priority determined based on the access count, and schedule the block and the superblock sequentially in a sorted order).
Jin does not specifically disclose: keeping only the access counts with unique address tags.
However, Jayasena discloses: keeping only the access counts with unique address tags (¶0058; the item's key may be marked as accessed in a Bloom Filter when it is accessed for the first time and, on a subsequent access, if the item is already found in the Bloom Filter, the item may be considered frequently-accessed. While this may result in false positives, that is acceptable as this is a performance optimization and will not affect correctness. In this variant, the Bloom Filter may be reset periodically to ensure only repeated accesses within a known and bounded time interval are considered frequent accesses. Alternatively, more sophisticated approximate set membership tracking structures, such as Counting Bloom Filters, may be used to keep an approximate count of accesses (and not just the fact the item was accessed at least once before) and enforce a threshold number of accesses above which an item is considered frequently-accessed).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine Jin and Jeyasena’s bloom filters to track the frequency of access. Jayesena optimizes performance (¶0058).
Per claim 2, Jeyasena discloses: wherein the first processing stage comprises a counting bloom filter (CBF) to receive an address tag for each memory access, pre-filter the first number of access counts, and output a tuple for each memory access, each tuple comprising a count value and the associated address tag corresponding to the respective memory access (¶0025, ¶0058; the item's key may be marked as accessed in a Bloom Filter when it is accessed for the first time and, on a subsequent access, if the item is already found in the Bloom Filter, the item may be considered frequently-accessed…Alternatively, more sophisticated approximate set membership tracking structures, such as Counting Bloom Filters, may be used to keep an approximate count of accesses (and not just the fact the item was accessed at least once before) and enforce a threshold number of accesses above which an item is considered frequently-accessed; the examiner notes that a tuple is merely an ordered record/list).
Per claim 11, Jin discloses: receive an indication of a memory access at the memory controller, the memory access being directed to a memory location; update and record multiple copies of access counts targeting a logical grouping of memory locations; (col. 14; profile an access count of a block in a control flow of a program code; determine that the block is an important block in response to an edge count of an edge entering the block being greater than or equal to a predetermined value, the edge count being included in the access count; schedule the important block in the pipeline based on the access count to prevent a register writeback conflict, schedule an operation absent executing writeback in a cycle in which the register writeback conflict is expected in the important block;) continuously sort the multiple copies of access counts and their associated address tags corresponding to the logical grouping of memory locations, (col. 14; form a superblock from the block based on the access count; sort the block and the superblock according to a priority determined based on the access count, and schedule the block and the superblock sequentially in a sorted order).
Jin does not specifically disclose: a first interface coupled to one or more host devices; a second interface coupled to one or more memory devices; a memory controller operatively coupled to the first interface and the second interface; and access tracking logic coupled to or part of the memory controller, wherein the access tracking logic is to; keeping only the multiple copies of access counts with unique address tags.
However, Jayasena discloses: a first interface coupled to one or more host devices; a second interface coupled to one or more memory devices; a memory controller operatively coupled to the first interface and the second interface; and access tracking logic coupled to or part of the memory controller, wherein the access tracking logic is to: (fig. 2; ¶0031; the computing device includes memory 200 such as a cache and the main memory of a processor such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), application specific integrated circuit (ASIC), or other integrated circuit, that includes a hash table 202 and a hash table logic 204. The hash table logic 204 interfaces with the memory 200 to populate and organize the hash table 202. )keeping only the multiple copies of access counts with unique address tags (¶0058; the item's key may be marked as accessed in a Bloom Filter when it is accessed for the first time and, on a subsequent access, if the item is already found in the Bloom Filter, the item may be considered frequently-accessed. While this may result in false positives, that is acceptable as this is a performance optimization and will not affect correctness. In this variant, the Bloom Filter may be reset periodically to ensure only repeated accesses within a known and bounded time interval are considered frequent accesses. Alternatively, more sophisticated approximate set membership tracking structures, such as Counting Bloom Filters, may be used to keep an approximate count of accesses (and not just the fact the item was accessed at least once before) and enforce a threshold number of accesses above which an item is considered frequently-accessed).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine Jin and Jeyasena’s bloom filters to track the frequency ofaccess. Jayesena optimizes performance (¶0058).
Per claim 16, Jin discloses: a processing pipeline comprising a first processing stage to update and record a first number of access counts targeting a logical grouping of memory locations (col. 14; profile an access count of a block in a control flow of a program code; determine that the block is an important block in response to an edge count of an edge entering the block being greater than or equal to a predetermined value, the edge count being included in the access count; schedule the important block in the pipeline based on the access count to prevent a register writeback conflict, schedule an operation absent executing writeback in a cycle in which the register writeback conflict is expected in the important block;) and a second processing stage to continuously sort the first number of access counts and their associated address tags corresponding to the logical grouping of memory locations (col. 14; form a superblock from the block based on the access count; sort the block and the superblock according to a priority determined based on the access count, and schedule the block and the superblock sequentially in a sorted order).
Jin does not specifically disclose: a memory device; and a memory controller coupled to the memory device via a channel, wherein the memory controller comprises a register file to store an output array of access counts corresponding to a set of logical grouping of memory locations, wherein the memory controller comprises:, keeping only the access counts with unique address tags.
However, Jayasena discloses: a memory device; and a memory controller coupled to the memory device via a channel, wherein the memory controller comprises a register file to store an output array of access counts corresponding to a set of logical grouping of memory locations, wherein the memory controller comprises:, s (fig. 2; ¶0031; the computing device includes memory 200 such as a cache and the main memory of a processor such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), application specific integrated circuit (ASIC), or other integrated circuit, that includes a hash table 202 and a hash table logic 204. The hash table logic 204 interfaces with the memory 200 to populate and organize the hash table 202. ) keeping only the access counts with unique address tag (¶0058; the item's key may be marked as accessed in a Bloom Filter when it is accessed for the first time and, on a subsequent access, if the item is already found in the Bloom Filter, the item may be considered frequently-accessed. While this may result in false positives, that is acceptable as this is a performance optimization and will not affect correctness. In this variant, the Bloom Filter may be reset periodically to ensure only repeated accesses within a known and bounded time interval are considered frequent accesses. Alternatively, more sophisticated approximate set membership tracking structures, such as Counting Bloom Filters, may be used to keep an approximate count of accesses (and not just the fact the item was accessed at least once before) and enforce a threshold number of accesses above which an item is considered frequently-accessed).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine Jin and Jeyasena’s bloom filters to track the frequency of access. Jayesena optimizes performance (¶0058).
Per claim 17, Jeyasena discloses: wherein the first processing stage comprises a counting bloom filter (CBF) to receive an address tag for each memory access, pre-filter the first number of access counts, and output a tuple for each memory access, each tuple comprising a count value and the associated address tag corresponding to the respective memory access (¶0025, ¶0058; the item's key may be marked as accessed in a Bloom Filter when it is accessed for the first time and, on a subsequent access, if the item is already found in the Bloom Filter, the item may be considered frequently-accessed…Alternatively, more sophisticated approximate set membership tracking structures, such as Counting Bloom Filters, may be used to keep an approximate count of accesses (and not just the fact the item was accessed at least once before) and enforce a threshold number of accesses above which an item is considered frequently-accessed; the examiner notes that a tuple is merely an ordered record/list).
Per claim 20, Jeyasena disclsoses: wherein the memory device is a dynamic random-access memory (DRAM) device (¶0065; Memory system 906 includes memory devices used by the computing system 900, such as random-access memory (RAM) modules; i.e. DRAM)
Claim(s) 3-4, 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin 9207922 herein Jin and Jayasena 20210182262 herein Jayasena in view of Kalamatianos et al. 11550588 herein Kalamatianos.
Per claim 3, the combined teachings of Jin and Jayasena does not specifically disclose: wherein the first processing stage is to update and record the multiple copies of access counts over a configurable time interval.
However, Kalamatianos discoses: wherein the first processing stage is to update and record the multiple copies of access counts over a configurable time interval (fig. 2, comp page access table, col. 3; the processor 100 includes an instruction pipeline having an instruction fetch stage 102 and additional pipeline stages (not shown). The additional pipeline stages include stages to decode fetched instructions into sets of operations, execution stages to execute the decoded operations, and a retire stage to retire executed instructions).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine Jin, Jeyasena and Kalamatianos’s filtering of the branch target buffers to reduces unnecessary access to lower-level caches. Kalamatianos reduces power without reducing branch prediction accuracy (col. 2 lines 45-55).
Per claim 4, Kalamatianos discloses: wherein the logical grouping of memory locations is a page, and wherein the associated address tags are page tags (fig. 2, col. 4; In response to receiving a fetched instruction address, the branch prediction control module 120 identifies the memory page corresponding to the fetched instruction address and identifies the count corresponding to the identified memory page. In response to the count being below a threshold, the branch prediction control module 120 provides the fetched instruction address to the L2 BTB 114 concurrent with identifying if the fetched instruction address hits in the L1 BTB 112. In response to a hit at the L2 BTB 114, the branch prediction control module 120 retrieves a branch target address (BTA) from the identified entry of the L2 BTB 114 and provides the BTA to the instruction fetch stage 102).
Claim 18 is the controller claim corresponding to the system claim 3-4 and is rejected under the same reasons set forth in connection with the rejection of claims 3-4.
Per claim 5, Kalamatianos discloses: wherein a size page of the page is approximately 2 mebibyte (2 MiB) or less (col. 6; In some embodiments, the size of each of the memory pages 231, 232 are configurable by a user or programmer of the processor 100; the examiner notes that the size can be any size encompassing 2 mebibyte. Further, mebibyte is merely a megabyte in computing terms).
Per claim 13, Kalamatianos discloses: wherein the logical grouping of memory locations is a page, and wherein the associated address tags are page tags (fig. 2, col. 4; In response to receiving a fetched instruction address, the branch prediction control module 120 identifies the memory page corresponding to the fetched instruction address and identifies the count corresponding to the identified memory page. In response to the count being below a threshold, the branch prediction control module 120 provides the fetched instruction address to the L2 BTB 114 concurrent with identifying if the fetched instruction address hits in the L1 BTB 112. In response to a hit at the L2 BTB 114, the branch prediction control module 120 retrieves a branch target address (BTA) from the identified entry of the L2 BTB 114 and provides the BTA to the instruction fetch stage 102).
Claim(s) 6, 10, 12 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin 9207922 herein Jin and Jayasena 20210182262 herein Jayasena in view of Aguilar Saborit et al. 20090028433 herein Saborit.
Per claim 6, the combined teachings of Jin and Jayasena does not specifically disclose: the first processing stage comprises a counting bloom filter (CBF) to pre-filter the first number of access counts over a configurable time interval, the CBF to output a tuple on each memory access, the tuple comprising a count value and an address tag; and the second processing stage comprises a tuple sorting pipeline to receive the tuples from the CBF and continuously sort the first number of tuples over the configurable time interval, the tuple sorting pipeline to output a snapshot of sorted tuples at the end of the configurable time interval.
However, Saborit discloses: the first processing stage comprises a counting bloom filter (CBF) to pre-filter the first number of access counts over a configurable time interval, the CBF to output a tuple on each memory access, the tuple comprising a count value and an address tag; (¶0018; means for creating in a build phase, during execution of a group by operation, for each group of tuples, a Counting Bloom Filter for each distinct column; and means for reviewing in a probe phase, once the group by operation is finished, the count values in the Counting Bloom Filter for each distinct column, and if the count value for a distinct column is greater than one, then sending the identified duplicate values to the distinct hash operator) and the second processing stage comprises a tuple sorting pipeline to receive the tuples from the CBF and continuously sort the first number of tuples over the configurable time interval, the tuple sorting pipeline to output a snapshot of sorted tuples at the end of the configurable time interval (¶0028; code for querying the values of the distinct columns in their respective Counting Bloom Filters for each tuple in a group, and if the lowest of the counters for a given value is one, then determining that the value is unique, and passing the value to the aggregate operator and bypassing the distinct hash operator; code for probing a value into a distinct hash table if the value is not bypassed, and if a match is found, discarding the value; if a match is not found, turning the probing into an insertion; code for traversing the distinct hash tables after finishing the processing of the tuples in the group, and flowing the distinct values up to the aggregate operator).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine Jin, Jeyasena and Saborit’s counting bloom filter for monitoring duplicates. Saborit reduces hash operator processing (¶0009).
Per claim 10, Saborit discloses: wherein the second processing stage comprises inline sorting logic to provide an access count array with a number of sorted tuples during a configurable time interval, each tuple of the number of tuples comprises a count value and an address tag (¶0028; code for querying the values of the distinct columns in their respective Counting Bloom Filters for each tuple in a group, and if the lowest of the counters for a given value is one, then determining that the value is unique, and passing the value to the aggregate operator and bypassing the distinct hash operator; code for probing a value into a distinct hash table if the value is not bypassed, and if a match is found, discarding the value; if a match is not found, turning the probing into an insertion; code for traversing the distinct hash tables after finishing the processing of the tuples in the group, and flowing the distinct values up to the aggregate operator).
Per claim 12, Saborit discloses: wherein the access tracking logic comprises: a counting bloom filter (CBF) to receive the indication of the memory access and output a tuple comprising a count value and an address tag corresponding to the memory access; a tuple sorting pipeline to receive the tuple from the CBF and continuously sort a first number of tuples over a configurable time interval, the tuple sorting pipeline to output a snapshot of sorted tuples at the end of the configurable time interval (¶0028; code for querying the values of the distinct columns in their respective Counting Bloom Filters for each tuple in a group, and if the lowest of the counters for a given value is one, then determining that the value is unique, and passing the value to the aggregate operator and bypassing the distinct hash operator; code for probing a value into a distinct hash table if the value is not bypassed, and if a match is found, discarding the value; if a match is not found, turning the probing into an insertion; code for traversing the distinct hash tables after finishing the processing of the tuples in the group, and flowing the distinct values up to the aggregate operator).
Per claim 19, Saborit discloses: wherein the access tracking logic comprises: a counting bloom filter (CBF) to receive the indication of the memory access and output a tuple comprising a count value and an address tag corresponding to the memory access; a tuple sorting pipeline to receive the tuple from the CBF and continuously sort a first number of tuples over a configurable time interval, the tuple sorting pipeline to output a snapshot of sorted tuples at the end of the configurable time interval (¶0028; code for querying the values of the distinct columns in their respective Counting Bloom Filters for each tuple in a group, and if the lowest of the counters for a given value is one, then determining that the value is unique, and passing the value to the aggregate operator and bypassing the distinct hash operator; code for probing a value into a distinct hash table if the value is not bypassed, and if a match is found, discarding the value; if a match is not found, turning the probing into an insertion; code for traversing the distinct hash tables after finishing the processing of the tuples in the group, and flowing the distinct values up to the aggregate operator).
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin 9207922 herein Jin, Jayasena 20210182262 herein Jayasena and Aguilar Saborit et al. 20090028433 herein Saborit in further view of Wang et al. 20220121365 herein Wang.
Per claim 7, the combined teachings of Jin Jayasena and Saborit does not specifically disclose: wherein the tuple sorting pipeline is to store the snapshot of sorted tuples in an output array having a second number of snapshots of sorted tuples.
However, Wang discloses: wherein the tuple sorting pipeline is to store the snapshot of sorted tuples in an output array having a second number of snapshots of sorted tuples (¶0119; Also at step 632, a snapshot of the data object may be captured. The snapshot of the data object may be encoded in the B-Tree mappings, via snapshot key-value pairs. A snapshot key may indicate a snapshot identifier (snapshot_ID) and a logical address of the data). A snapshot value for the key may indicate a chunk identifier for where the data of the logical address is included in. The snapshot captured at step 630 may be a first snapshot. Updated data may be received and a second snapshot of the data may be captured. The snapshot key-value pairs may be encoded in a B-Tree that sorts n-tuple representations of the snapshot key-value pairs via a common snapshot identifier).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine Jin, Jeyasena, Saborit’s and Wang’s snapshots to recover from failures. Wang provides low latency recover (Abstract: The techniques also provide low-latency recovery and/or system rollback in the event of any failure in the SDDC.).
Per claim 14, Saborit discloses: wherein the tuple sorting pipeline is to store the snapshot of sorted tuples in an output array having a second number of snapshots of sorted tuples (¶0119; Also at step 632, a snapshot of the data object may be captured. The snapshot of the data object may be encoded in the B-Tree mappings, via snapshot key-value pairs. A snapshot key may indicate a snapshot identifier (snapshot_ID) and a logical address of the data). A snapshot value for the key may indicate a chunk identifier for where the data of the logical address is included in. The snapshot captured at step 630 may be a first snapshot. Updated data may be received and a second snapshot of the data may be captured. The snapshot key-value pairs may be encoded in a B-Tree that sorts n-tuple representations of the snapshot key-value pairs via a common snapshot identifier).
Claim(s) 8, 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin 9207922 herein Jin, Jayasena 20210182262 herein Jayasena and Aguilar Saborit et al. 20090028433 herein Saborit and Wang et al. 20220121365 herein Wang in further view of Billyard 20170011487 herein Billyard.
Per claim 8, the combined teachings of Jin Jayasena and Saborit does not specifically disclose: wherein the output array is stored in a register file accessible by software.
However, Billyard discloses: wherein the output array is stored in a register file accessible by software (¶0095; It is presented to the application as a linear register file of N 4-tuples where N is typically >128. This register file is used in any way the application sees fit, meaning this embodiment of the present invention needs to process this file carefully to ensure the entire register file is not transmitted every time a shader is used, for example.).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine Jin, Jeyasena, Saborit, Wang and Bllyard’s register files to improve bandwidth (¶0013; an interactive graphics streaming system is desired which provides improved use of the bandwidth between the server and client, is adaptable to different client device capabilities, and requires minimal or no reprogramming of the interactive graphics application).
Per claim 9, Jayasena discloses: wherein the processing pipeline is reset responsive to receiving a reset signal (¶0058; In this variant, the Bloom Filter may be reset periodically to ensure only repeated accesses within a known and bounded time interval are considered frequent accesses. Alternatively, more sophisticated approximate set membership tracking structures, such as Counting Bloom Filters, may be used to keep an approximate count of accesses (and not just the fact the item was accessed at least once before) and enforce a threshold number of accesses above which an item is considered frequently-accessed).
Per claim 15, Billyard discloses: wherein the output array is stored in a register file accessible by software (¶0095; It is presented to the application as a linear register file of N 4-tuples where N is typically >128. This register file is used in any way the application sees fit, meaning this embodiment of the present invention needs to process this file carefully to ensure the entire register file is not transmitted every time a shader is used, for example.).
Response to Arguments
Applicant's arguments filed 2/26/26 have been fully considered but they are not persuasive.
The applicant argues: Jin's "access count" is fundamentally different from "access counts targeting a logical grouping of memory locations" as recited by claim 1.…A program control-flow block is not a physical or logical grouping of memory locations. In contrast, claim 1 recites "access counts targeting a logical grouping of memory locations." Jin does not disclose, suggest, or contemplate tracking access frequency of memory pages or other logical memory groupings. Jin explicitly states that "the control flow may imply a plurality of blocks according to a program code, and in each block, a row direction may denote an order of cycles in which an operation is executed…. Moreover, even assuming arguendo that Jin discloses a "processing pipeline," Jin does not disclose a memory controller comprising such a pipeline, nor does Jin disclose that the pipeline operates on memory accesses directed to logical groupings of memory locations."
Jin discloses "a block scheduling unit which may sort a block and a superblock according to a priority determined based on the access count, and may schedule the block and the superblock sequentially in a sorted order." See Jin, col. 14, lines 25-30. This sorting of code blocks for compiler scheduling is fundamentally different from the claimed feature of a second processing stage that continuously sorts access counts and their associated address tags corresponding to logical groupings of memory locations, while keeping only the access counts with unique address tags. Jin sorts program blocks based on priority for execution scheduling purposes. Jin does not disclose continuously sorting memory access counts, does not disclose maintaining a sorted structure of memory access telemetry, and does not disclose keeping only the access counts with unique address tags, as required by claim 1.
The examiner respectfully disagrees and asserts that Jin does disclose logical memory groupings as claimed. A block is precisely a grouping of memory addresses. Further, the examiner disagrees with the applicant characterization of the Jin reference. The applicant seems to suggest the Jin reference isn’t about a memory block because of the use of the memory. The examiner notes that the code is reference in memory as taught by Jin. An access count of the block comprised with code are tracked according to the claim limitation. All of this access tracking is happening in a processing pipeline. There is nothing in the claim that precludes a specific usage of the memory. The only requirement is that the blocks are tracked for access.
The applicant also makes the point that Jin doesn’t disclose a memory controller for reason addressed above. The examiner disagrees and asserts that Jin clearly discloses a memory controller in claim 9 reproduced here: “A compiling apparatus for scheduling a block in a pipeline, the compiling apparatus comprising: a memory; a processor operatively coupled with the memory, the processor configured to: profile an access count of a block in a control flow of a program code; determine that the block is an important block in response to an edge count of an edge entering the block being greater than or equal to a predetermined value, the edge count being included in the access count.”
The applicant further argues that Jim does not disclose sorting of a second processing stage that continuously sorts access counts and their associated tags. The examiner respectfully disagrees and asserts that Jim does disclose sorting as claimed. The claim merely requires sorting based on access counts. Jin discloses sorting the blocks and superblocks according to a priority based on access counts and scheduling the blocks and superblocks sequentially in the sorted order. Jayasena is relied upon to teach keeping only the access counts with unique address tags. Jeyasena’s bloom filter tracks frequently access items. Items that a considered frequently access based on access counts are maintained in the bloom filter.
The applicant argues that Jeyasena does not disclose keeping only the access counts with unique address. The examiner respectfully disagrees and asserts that the claim merely requires identifying duplicate addresses and only storing the first instance of the access counts address. Further, the examiner notes that the claim limitation is an intended result and does not specifically disclose a process achieving the result. Jeyasena discloses a Bloom Filter when accessed for the first time to track access in memory stores an entry. Any subsequent entry is track by keeping a counter. Essentially only a unique tag occupies an entry and a subsequent access is directed to the previous entry by tracking by incrementing an access count. Therefore, Jeyasena discloses keeping only the access counts with unique address.
The applicant argues: The Office Action asserts that it would have been obvious to combine Jin and Jayasena to track frequency of access. However, the Office Action does not provide an articulated reasoning explaining how or why one of ordinary skill would modify Jin's compiler scheduling apparatus with Jayasena's hash table Bloom filter techniques to produce a memory controller having hardware-based page-level access telemetry. Jin addresses compiler instruction scheduling and register writeback conflicts, while Jayasena addresses hash table bucket management. Neither reference concerns memory controller architecture nor page-level access tracking. The rejection therefore lacks the required rational underpinning to support the proposed combination.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Jeyasena’s bloom filters are combined with Jins to track the frequency of access. Jayesena optimizes performance.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights