DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 10/22/2024. Claims 2-21 are presented for examination and have been considered below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 12,142,332 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every limitations claimed in the present application is anticipated by the claimed invention of U.S. Patent No. 12,142,332 B2, as follows:
Present application
US12,142,332 B2
2. An apparatus, comprising: a memory system configured to route signals between different regions of the memory system; a first substrate comprising a first interface coupled with the memory system and a probe interface, the first substrate comprising a resistor coupled with the memory system; and a second substrate coupled with a second interface of the first substrate and configured to receive a signal of the memory system from the first interface.
3. The apparatus of claim 2, wherein: the memory system is located above a first surface of the first substrate in a vertical direction; and a second surface of the first substrate is located above a first surface of the second substrate in the vertical direction.
The apparatus of claim 2, comprising: a set of first conductive lines coupled with the first interface and the second interface, the set of first conductive lines configured to communicate the signal of the memory system from the first interface to the second interface; and a second conductive line coupled with the first interface and the probe interface, the second conductive line configured to communicate the signal from the first interface to the probe interface.
The apparatus of claim 2, wherein: the first
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substrate further comprises a first surface coupled with the memory system and that includes the first interface and the probe interface, the resistor is coupled with the first surface.
The apparatus of claim 2, wherein the resistor is coupled with the first interface of the first substrate and a contact of the probe interface.
The apparatus of claim 6, wherein a size of the resistor is based at least in part on an impedance between the memory system and the contact of the probe interface.
The apparatus of claim 2, further comprising: a host system associated with the memory system coupled with the second substrate, the second substrate configured to route signals associated with the memory system between the first substrate and the host system.
The apparatus of claim 8, further comprising: a third set of conductive lines coupled with the host system and an interface of the second substrate, the third set of conductive lines configured to communicate the signals associated with the memory system between the host system and the interface of the second substrate prior to the second substrate routing the signals between the first substrate and the host system.
10. The apparatus of claim 2, further comprising: a component configured to couple with the probe interface and configured to measure the signal routed by the first substrate to the probe interface.
The apparatus of claim 10, wherein the component is further configured to determine an error associated with the memory system based at least in part on measuring the signal.
The apparatus of claim 10, wherein the resistor is configured to isolate an impedance of the component from the memory system.
The apparatus of claim 2, wherein the resistor comprises a surface- mount chip resistor.
14. The apparatus of claim 2, wherein the resistor comprises a resistor that is buried in the first substrate.
15. An apparatus, comprising: a first interface coupled with a first surface of a first substrate and configured to couple with a memory system; a second interface coupled with a second surface of the first substrate and configured to couple with a second substrate that is coupled with a host system; and a third interface coupled with the first surface of the first substrate and coupled with the first interface, the third interface comprising a resistor coupled with the first surface of the first substrate and configured to output a signal of the memory system.
16. The apparatus of claim 15, further comprising: a set of first conductive lines coupled with the first interface and the second interface, the set of first conductive lines configured to communicate the signal of the memory system from the first interface to the second interface; and a second conductive line coupled with the first interface and the third interface, the second conductive line configured to communicate the signal from the first interface to the third interface.
17. The apparatus of claim 15, wherein the first interface is located below the first surface of the first substrate and the third interface is located above the first surface of the first substrate.
18. A memory system, comprising: a plurality of substrates comprising at least a first substrate; one or more interfaces associated with the plurality of substrates; an isolation resistor coupled with the first substrate; and processing circuitry coupled with the one or more interfaces and the isolation resistor and configured to cause the memory system to: communicate, by the one or more interfaces, a signal from the memory system to a host system; and isolate, by the isolation resistor coupled with the first substrate, an impedance associated with the signal based on communicating the signal from the memory system to the host system via the plurality of substrates.
19. The memory system of claim 18, wherein the one or more interfaces comprise a resistor coupled with a first surface of a first substrate, wherein the processing circuitry is further configured to cause the memory system to: output, by the one or more interfaces, the signal to the host system.
20. The memory system of claim 19, wherein the one or more interfaces are configured to couple with a test component and output the signal to the test component.
21. The memory system of claim 20, wherein the resistor is further configured to isolate an impedance of the test component from the memory system.
1. An apparatus, comprising: a memory system comprising contacts configured to route signals to different regions of the memory system; a first substrate comprising a memory system interface coupled with the memory system and a probe interface, the first substrate configured to route a signal of the memory system to the probe interface, the first substrate comprising a resistor coupled with the contacts of the memory system; and a second substrate coupled with a host system interface of the first substrate and configured to receive the signal of the memory system from the memory system interface.
2. The apparatus of claim 1, wherein: the first substrate further comprises a first surface coupled with the memory system and that includes the memory system interface and the probe interface, the resistor is coupled with the first surface.
3. The apparatus of claim 1, wherein the resistor is coupled between a first contact of the memory system interface of the first substrate and a second contact of the probe interface.
4. The apparatus of claim 3, wherein a size of the resistor is based at least in part on an impedance between the first contact and the second contact.
5. The apparatus of claim 1, wherein: the contacts are arranged with a pitch; and a size of the resistor is based at least in part on the pitch of the contacts.
6. The apparatus of claim 1, further comprising: a host system associated with the memory system coupled with the second substrate, the second substrate configured to route signals associated with the memory system between the first substrate and the host system.
7. The apparatus of claim 1, further comprising: a tester configured to couple with the probe interface and configured to measure the signal routed by the first substrate to the probe interface.
8. The apparatus of claim 7, wherein the tester is further configured to determine an error associated with the memory system based at least in part on measuring the signal.
9. The apparatus of claim 7, wherein the resistor is configured to isolate an impedance of the tester from the memory system.
10. The apparatus of claim 1, wherein the first substrate further comprises a conductive line coupled with the resistor and the probe interface.
11. The apparatus of claim 1, wherein: the first substrate comprises a second resistor; and the resistor has a first resistance the second resistor has a second resistance different than the first resistance.
12. The apparatus of claim 1, wherein the resistor comprises a surface-mount chip resistor.
13. The apparatus of claim 1, wherein the resistor comprises a 01005 component.
14. An apparatus, comprising: a first substrate; a first interface coupled with a first surface of the first substrate and configured to couple with contacts of a memory system; a second interface coupled with a second surface of the first substrate and configured to couple with a second substrate that comprises a host system associated with the memory system; and a third interface coupled with the first surface of the first substrate and coupled with the first interface, the third interface configured to output a signal of the memory system occurring at the contacts, the third interface comprising a resistor coupled with the first surface of the first substrate.
15. The apparatus of claim 14, wherein the third interface is further configured to couple with a tester and output the signal of the memory system to the tester.
16. The apparatus of claim 15, wherein the resistor is further configured to isolate an impedance of the tester from the memory system.
17. The apparatus of claim 14, wherein the third interface comprises a plurality of resistors coupled with the first surface and coupled with the contacts of the memory system.
18. The apparatus of claim 14, wherein the third interface comprises a conductive line coupled with the resistor and a probe point of the third interface, the signal outputted at the probe point.
19. The apparatus of claim 14, wherein: the third interface is configured to comprise a second resistor; and the resistor has a first resistance the second resistor has a second resistance different than the first resistance.
20. A system, comprising: a device-under-test comprising: a memory system; a first substrate comprising a first interface coupled with the memory system and configured to route a signal of the memory system from the first interface to a second interface of the first substrate and a third interface of the first substrate, the first substrate comprising a resistor on a first surface of the first substrate; a second substrate coupled with the second interface of the first substrate; and a host system coupled with the second substrate; and a tester comprising a probe that is configured to couple with the third interface of the first substrate, the tester configured to measure the signal of the memory system.
21. The system of claim 20, wherein the resistor is configured to isolate an 2 impedance of the tester from the memory system.
22. The system of claim 20, wherein the resistor comprises a surface-mount chip resistor.
23. The system of claim 20, wherein the tester is configured to determine an error associated with the memory system based at least in part on measuring the signal of the memory system.
24. The system of claim 20, wherein the tester is configured to determine an absence of errors associated with the memory system based at least in part on measuring the signal of the memory system.
25. The system of claim 20, wherein the second substrate is configured to 2 communicate signals between the host system and the memory system.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-16 are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 2012/0013346 A1) and further in view of Tektronix Application Note (“Electrical Verification of DDR Memory,” Tektronix, 2013).
Claim 2: Xu teaches a signal test device for motherboard DDR bus testing comprising a first substrate (PCB 10), a first interface (connector 20 with connection pins), a probe interface (signal test point TP1), and a resistor (first resistor R1 = 20Ω) coupled with the memory system. The resistor is coupled with the first interface and a contact of the probe interface, wherein the size of the resistor is based at least in part on impedance matching between the memory system and the probe contact (matching impedance between signal line of motherboard and signal line of test device). Xu further teaches a component (oscilloscope) coupled with the probe interface to measure signals and determine errors, wherein the resistor isolates the impedance of the component from the memory system. Xu also teaches a surface-mount chip resistor (R1) (e.g. see ¶¶0014, 0016-0018, FIGS. 1, 3).
Not explicitly taught by Xu is a second substrate as claimed.
However, Tektronix teaches memory component interposers for DDR probing comprising a first substrate (interposer) with a first interface (top side BGA footprint) coupled with a memory system (DRAM), a second interface (bottom side BGA footprint) coupled with a second substrate (motherboard or DIMM socket), and a probe interface (solder-down test points). The interposer includes isolation resistors “embedded within the interposer, as close as possible to the BGA pads of the memory component,” wherein the resistors “are matched to the P7500 probe tip’s electrical network, ensuring excellent signal fidelity” and “isolate the DDR4 signal and the probe loading effect.” The interposer routes signals from the memory system to the host system and to the test points. Conductive lines from the first interface to the second interface and from the first interface to the probe interface are inherent in the interposer design. The memory system is located above the first surface; the second surface of the interposer is above the first surface of the second substrate (e.g. See pp. 3-5, 15; FIGS. 5, 7).
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to modify Xu’s test device to include a second interface and substrate (i.e., to convert Xu’s plug-in module into an interposer) because interposers were well-known, conventional solution for accessing BGA signals. This is merely a simple substitution of one known element (interposer structure) for another (plug-in module) to achieve the predictable result of enabling signal access while preserving system functionality.
Claim 3: Xu and Tektronix teach the apparatus of claim 2, wherein: the memory system is located above a first surface of the first substrate in a vertical direction (e.g. Tektronix teaches that DRAM is soldered to top side of interposer, located above first surface: pp. 3-5); and a second surface of the first substrate is located above a first surface of the second substrate in the vertical direction (e.g. Tektronix teaches that bottom side of interposer is above top surface of motherboard/socket when mounted, pp. 3-5).
Claim 4: Xu and Tektronix teach the apparatus of claim 2, comprising: a set of first conductive lines coupled with the first interface and the second interface, the set of first conductive lines configured to communicate the signal of the memory system from the first interface to the second interface (e.g. Tektronix teaches traces through interposer from top BGA pads to bottom BGA pads which is inherent in interposer function, pp. 3-5 ); and a second conductive line coupled with the first interface and the probe interface, the second conductive line configured to communicate the signal from the first interface to the probe interface (e.g. Xu teaches that traces on PCB 10 from connector pins to signal test points, in ¶¶0014, 0016, FIG. 3. And Tektronix teaches that traces from top BGA pads to test points on interposer, in pp. 3-5).
Claim 5: Xu and Tektronix teach the apparatus of claim 2, wherein: the first
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substrate further comprises a first surface coupled with the memory system and that includes the first interface and the probe interface, the resistor is coupled with the first surface (e.g. Xu teaches, in ¶¶0013, 0016, FIG. 3, that connector 20 and signal test point TP1 are on PCB 10; R1 is coupled on PCB and Tektronix teaches, in pp. 3-5, that top surface of interposer includes BGA pads (first interface) and test points (probe interface); resistors are embedded in/on interposer near top surface).
Claim 6: Xu and Tektronix teach the apparatus of claim 2, wherein the resistor is coupled with the first interface of the first substrate and a contact of the probe interface (e.g. Xu teaches, in ¶¶0016-0017, FIG. 3, that R1 is connected between connector pin (first interface) and signal test point TP1 (probe interface contact) and Tektronix teaches, in pp. 3-5, that isolation resistors are connected between BGA pads (first interface) and test point pads (probe interface contact)).
Claim 7: Xu and Tektronix teach the apparatus of claim 6, wherein a size of the resistor is based at least in part on an impedance between the memory system and the contact of the probe interface (e.g. Xu teaches, in ¶0017], that R1 is 20Ω to “match impedance between a signal line of the motherboard and a signal line of the signal test device and Tektronix teaches, in p. 4, that Resistors “are matched to the P7500 probe tip’s electrical network” and “isolate the DDR4 signal and the probe loading effect).
Claim 8: Xu and Tektronix teach the apparatus of claim 2, further comprising: a host system associated with the memory system coupled with the second substrate, the second substrate configured to route signals associated with the memory system between the first substrate and the host system (e.g. Motherboard (host system) has DIMM slot that receives connector 20. See Xu, ¶0014) and motherboard (host system) is coupled to socket/second substrate; socket routes signals between interposer and host. See Tektronix, pp. 3-5).
Claim 9: Xu and Tektronix teach the apparatus of claim 8, further comprising: a third set of conductive lines coupled with the host system and an interface of the second substrate, the third set of conductive lines configured to communicate the signals associated with the memory system between the host system and the interface of the second substrate prior to the second substrate routing the signals between the first substrate and the host system (e.g. Motherboard traces to DIMM socket; socket interface receives signals from host before routing to interposer; inherent features in Tektronix pp. 3-5).
Claim 10: Xu and Tektronix teach the apparatus of claim 2, further comprising: a component configured to couple with the probe interface and configured to measure the signal routed by the first substrate to the probe interface (e.g. Oscilloscope coupled to signal test point TP1 to “collect data signals”. See Xu ¶0018. And Oscilloscope probe coupled to interposer test points to “perform JEDEC-compliant measurements”. See Tektronix pp. 4-5).
Claim 11: Xu and Tektronix teach the apparatus of claim 10, wherein the component is further configured to determine an error associated with the memory system based at least in part on measuring the signal (e.g. Oscilloscope can determine signal transmission performance; error calculation shown (13.9mV difference, 0.97% error). See Xu, ¶0019, FIG. 4. And oscilloscope with DDRA software performs JEDEC compliance testing, pass/fail determination, failure analysis and debug. See Tektronix pp. 7-11).
Claim 12: Xu and Tektronix teach the apparatus of claim 10, wherein the resistor is configured to isolate an impedance of the component from the memory system. (e.g. R1 “can match impedance … to protect the signal transmission performance … from interfering”—inherently isolates probe loading. See Xu, ¶0017]. And resistors “isolate the DDR4 signal and the probe loading effect”. See Tektronix, p. 4).
Claim 13: Xu and Tektronix teach the apparatus of claim 2, wherein the resistor comprises a surface-mount chip resistor (e.g. R1 is a surface-mount resistor (inferred from PCB assembly; common knowledge) “Small isolation resistors”; surface-mount chip resistors are the conventional implementation).
Claim 14: Xu and Tektronix teach the apparatus of claim 2, wherein the resistor comprises a resistor that is buried in the first substrate (e.g. “Buried resistors placed at the signals inside the BGA interposer”. See Tektronix, p. 4).
Claim 15: Xu teaches an apparatus, comprising:
a first interface coupled with a first surface of a first substrate and configured to couple with a memory system (e.g. Connector 20 on PCB 10 coupled to motherboard DDR bus. See ¶¶0013-0014]);
a third interface coupled with the first surface of the first substrate and coupled with the first interface, the third interface comprising a resistor coupled with the first surface of the first substrate and configured to output a signal of the memory system (e.g. Signal test point TP1 on PCB 10, coupled to connector via R1, outputs DDR signal. See ¶¶0016-0018, FIG. 3]).
Not explicitly taught by Xu is a second interface coupled with a second surface of the first substrate and configured to couple with a second substrate that is coupled with a host system.
However, Tektronix teaches memory component interposers for DDR probing comprising a first substrate (interposer) with a first interface (top side BGA footprint) coupled with a memory system (DRAM), a second interface (bottom side BGA footprint) coupled with a second substrate (motherboard or DIMM socket), and a probe interface (solder-down test points). The interposer includes isolation resistors “embedded within the interposer, as close as possible to the BGA pads of the memory component,” wherein the resistors “are matched to the P7500 probe tip’s electrical network, ensuring excellent signal fidelity” and “isolate the DDR4 signal and the probe loading effect.” The interposer routes signals from the memory system to the host system and to the test points. Conductive lines from the first interface to the second interface and from the first interface to the probe interface are inherent in the interposer design. The memory system is located above the first surface; the second surface of the interposer is above the first surface of the second substrate (e.g. See pp. 3-5, 15; FIGS. 5, 7).
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to modify Xu’s test device to include a second interface and substrate (i.e., to convert Xu’s plug-in module into an interposer) because interposers were well-known, conventional solution for accessing BGA signals. This is merely a simple substitution of one known element (interposer structure) for another (plug-in module) to achieve the predictable result of enabling signal access while preserving system functionality.
Claim 16: Xu and Tektronix teach the apparatus of claim 15, further comprising: a set of first conductive lines coupled with the first interface and the second interface, the set of first conductive lines configured to communicate the signal of the memory system from the first interface to the second interface (e.g. Traces through interposer from top to bottom BGA pads—inherent. See Tektronix pp. 3-5); and a second conductive line coupled with the first interface and the third interface, the second conductive line configured to communicate the signal from the first interface to the third interface (e.g. Traces from connector pins to signal test points. See Xu, ¶¶0014, 0016, FIG. 3. And traces from BGA pads to test point pads. See Tektronix, pp. 3-5).
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/12/2026