DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 10/22/2024.
Claims 1-20 are pending. Claims 1, 8, and 15 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, Breadth of a claim is not to be equated with indefiniteness, but “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic priority details.
No Information Disclosure Statement (IDS)
5. No IDS is in the record as of this office action date.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention (See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968)). Such essential matter may include missing elements, steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention.
For example, regarding independent claim 1, omitted elements & associated limitations, omitted steps and necessary structural cooperative relationships of elements are highlighted in the following:
a mode register circuit coupled to the input/output circuit and configured to: (“mode register circuit” construction is missing and it is not clear what constitute mode register circuit that relates to various components in subsequent limitations)
determine a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; and (It is not clear what circuit and how it determines die configuration and a burst length since “mode register circuit” is not clear. Also “die configuration” is vague, generally it is related to number of DQ pins which is not described in the claim. This limitation is not sufficiently described in view of the spec)
determine at least one group of mode registers identified in the MRR-ALL command or the MRW-ALL command (It is not clear what circuit determines “group of mode registers”. It is not clear if “mode registers” are part of “mode register circuit” or not).
send mode register information associated with the at least one group of mode registers identified in the MRR-ALL command to the external controller over the DQ interface (“one group of mode registers identified” is not clear and how it relates to “mode register circuit”).
Similarly, claim 8 and claim 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. The omitted elements are description of “mode register circuit” construction; description of what circuit and how it determines die configuration and a burst length; description of “one group of mode registers identified”.
All dependent claims inclusive of claims 1-20 are rejected under this category. See art rejection for the interpretation of the art rejected claims.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 1-2, 7-9, and 14-16 is/are rejected under 35 U.S.C. 103 as being obvious over Mai et al. (US 2019/0066790 A1), in view of Gans et al. (US 2020/0004420 A1).
Regarding independent claim 1, Mai teaches an apparatus (Fig. 1: 10 memory device), comprising:
an input/output circuit (Fig. 1: 16, 46, 14 combined. See I/O Interface, command interface, data path) configured to communicate with an external controller (para [0015]: “controller”),
wherein the input/output circuit comprises a command/address (CA) interface (Fig. 1: CA input with 14) and a data (DQ) interface (Fig. 1: DQ input/ output with 16); and
a mode register circuit (Fig. 1: 38, 32 combined. See mode register and command decoder) coupled to the input/output circuit (operably coupled to Fig. 1: 16, 14) and configured to:
decode, on the CA interface, a command from the external controller (Fig. 1 to Fig. 2 in context of para [0019], para [0020]: CA input, associated read/ write signals from external are decoded and transmitted to mode register),
wherein the command comprises a mode register read all (MRR-ALL) command or a mode register write all (MRW-ALL) command (Fig. 2 in context of para [0030], para [0031]: MRR, MRW command received by mode registers 0-N);
determine a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; and
determine at least one group of mode registers identified in the MRR-ALL command or the MRW-ALL command (Fig. 2: mode registers 0-N in context of para [0012]: “…respective mode register…respective memory component…” are identified from MRR, MRW received),
wherein the input/output circuit (Fig. 1: 16, 46, 14) is configured to send:
mode register information associated with the at least one group of mode registers identified in the MRR-ALL command to the external controller over the DQ interface (para [0024], Fig. 2: data path, DQ communication to memory bank. See Fig. 5: 94[Wingdings font/0xE0]96[Wingdings font/0xE0]98 and para [0038]).
Mai is silent with respect to “…determine a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command…”
Gans teaches –
determine (according to mode register read/ write command) a die configuration (para [0028]: “…information for operands corresponding to modes of bank architecture…” is used by mode register read/ write commands) and a burst length (para [0028]: “…information for operands corresponding to burst length…” is used by mode register read/ write commands) for executing the MRR-ALL command or the MRW-ALL command (see para [0028], para [0029]).
Mai and Gans are in the same field of endeavor of DDR memory operation and control using mode register read, write scheme and they are in analogous file of art. Since Gans also teaches apparatus (Fig. 2: 200 memory device), comprising: an input/output circuit (Fig. 2: 260 IO circuit) configured to communicate with an external controller (Fig. 1: 10), a mode register circuit (Fig. 2: 225 mode register) coupled to the input/output circuit (Fig. 2: 260 IO circuit). An ordinary skill in the art would understand the use of MRR, MRW commands compatible die configuration and burst length according to Gan’s teachings into the apparatus of Mai.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Gans into the teachings of Mai such that mode registers with enhanced functionality can be employed in order to “…meet the different memory operating requirements and configurations demanded…” (Gans para [0003])
Regarding claim 2, Mai and Gans teach the apparatus of claim 1. Mai teaches wherein the DQ interface comprises at least four DQs (Fig. 1: DQ<15:8>), and
wherein sending the mode register information over the DQ interface comprises sending information for at least four mode registers over the at least four DQs (Fig. 2: Mode Register 0-N and Fig. 1: DQ).
Regarding claim 7, Mai and Gans teach the apparatus of claim 1. Mai teaches wherein the apparatus is a dynamic random-access memory (DRAM) that is coupled to the external controller (see para [0010], para [0011], para [0015]: DRAM in DDR system and coupled controller).
Regarding independent claim 8, Mai teaches a memory system (Fig. 1 in context of para [0015]: memory system with controller and memory device), comprising:
a memory controller (para [0015]: “controller”); and
a memory array (Fig. 1: 12) operably coupled to the memory controller (para [0015]) and configured to:
decode a command from the memory controller (Fig. 1 to Fig. 2 in context of para [0019], para [0020]: CA input, associated read/ write signals, commands from external are decoded and transmitted to mode register),
wherein the command comprises a mode register read all (MRR-ALL) command or a mode register write all (MRW-ALL) command (Fig. 2 in context of para [0030], para [0031]: MRR, MRW command received by mode registers 0-N);
determine a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command;
determine at least one group of mode registers identified in the MRR-ALL command or the MRW-ALL command (Fig. 2: mode registers 0-N in context of para [0012]: “…respective mode register…respective memory component…” are identified from MRR, MRW received); and
send mode register information associated with the at least one group of mode registers identified in the MRR-ALL command to the memory controller (para [0024], Fig. 2: data path, DQ communication to memory bank. See Fig. 5: 94[Wingdings font/0xE0]96[Wingdings font/0xE0]98 and para [0038]).
Mai is silent with respect to “…determine a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command…”
Gans teaches –
determine (according to mode register read/ write command) a die configuration (para [0028]: “…information for operands corresponding to modes of bank architecture…” is used by mode register read/ write commands) and a burst length (para [0028]: “…information for operands corresponding to burst length…” is used by mode register read/ write commands) for executing the MRR-ALL command or the MRW-ALL command (see para [0028], para [0029]).
Mai and Gans are in the same field of endeavor of DDR memory operation and control using mode register read, write scheme and they are in analogous file of art. Since Gans also teaches apparatus (Fig. 2: 200 memory device), comprising: an input/output circuit (Fig. 2: 260 IO circuit) configured to communicate with an external controller (Fig. 1: 10), a mode register circuit (Fig. 2: 225 mode register) coupled to the input/output circuit (Fig. 2: 260 IO circuit). An ordinary skill in the art would understand the use of MRR, MRW commands compatible die configuration and burst length according to Gan’s teachings into the apparatus of Mai.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Gans into the teachings of Mai such that mode registers with enhanced functionality can be employed in order to “…meet the different memory operating requirements and configurations demanded…” (Gans para [0003]).
Regarding claim 9, Mai and Gans teach the memory system of claim 8, wherein the memory array comprises at least four DQs, and wherein sending the mode register information comprises sending information for at least four mode registers over the at least four DQs. (See claim 2 rejection analysis)
Regarding claim 14, Mai and Gans teach the memory system of claim 8, wherein the memory array is a dynamic random-access memory (DRAM). (See claim 7 rejection analysis)
Regarding independent claim 15, Mai and Gans teach a method of operating an apparatus, the method comprising:
decoding a command from an external controller,
wherein the command comprises a mode register read all (MRR-ALL) command or a mode register write all (MRW-ALL) command;
determining a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command;
determining at least one group of mode registers identified in the MRR-ALL command or the MRW-ALL command; and
sending mode register information associated with the at least one group of mode registers identified in the MRR-ALL command to the external controller.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
Regarding claim 16, Mai and Gans teach the method of claim 15, wherein the apparatus comprises at least four DQs, and wherein sending the mode register information comprises sending information for at least four mode registers over the at least four DQs. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 2, and is therefore rejected for the same reasons as claim 2).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
OH et al. (US 2021/0405927 A1): Fig. 1-Fig. 12 disclosure applicable for all claims. KANG (US 2018/0130506 A1): Fig. 1-Fig. 15 disclosure applicable for all claims.
Allowable Subject Matter
Claims 3-6, 10-13, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable (tentatively Indicated as Allowable) if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In addition, any associated 112b rejection of claims 1-20 must be over-come.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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