DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed October 22, 2024.
Claims 21-40 are pending. Claims 1-20 were canceled by Preliminary Amendments. Claims 21, 31 and 40 are independent.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 31 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 31 recites the limitations "the functional circuitry" in line 8 and “the logic” in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-22, 24, 30-32, 34 and 39-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suh et al. (U.S. 2019/0324850; hereinafter “Suh”).
Regarding independent claim 21, Suh discloses an apparatus (Fig. 1), comprising:
a functional circuitry (Fig. 1: 120);
a plurality of mode registers (MRs) coupled to the functional circuitry (Fig. 1: 180-1-180-M) and configured to store control data associated with operations of the functional circuitry (see page 6, par. 0059);
a communication circuit (Fig. 1: 130) coupled to the functional circuitry (Fig. 1: 160) and the plurality of MRs (Fig. 1: 180-1-180-M), the communication circuit configured to facilitate external communications for the functional circuitry (see page 3, par. 0028); and
a logic (Fig. 1: 160) coupled to the functional circuitry (Fig. 1: 120), the plurality of MRs (Fig. 1: 180-1-180-M), and the communication circuit (Fig. 1: 130), the logic configured to:
receive a single-access command through the communication circuit (see page 6, par. 0059);
in response to the single-access command, access one MR in the plurality of MRS (see page 6, par. 0059);
receive one group-access command through the communication circuit (see page 6, par. 0062); and
in response to the one group-access command, access the plurality of MRs (see page 6, par. 0062).
Regarding claim 22, Suh discloses wherein the one group-access command includes a group read command;
the logic is configured to read the control data from the plurality of MRs in response to the group read command; and
the communication circuit is configured to send the control data externally in response to the group read command (see page 6, par. 0059).
Regarding claim 24, Suh discloses wherein:
the one group-access command includes a group write command;
the communication circuit is configured to receive the control data along with the group write command; and
the logic is configured to store the control data across the plurality of mode registers in response to the group write command (see page 6, par. 0059).
Regarding claim 30, Suh discloses wherein the apparatus is a Dynamic Random Access Memory (DRAM) (see page 3, par. 0027); and
the communication circuit includes a data (DQ) interface, wherein the one group-access command is received through the DQ interface (Fig. 1: DQ, see also page 3, par. 0027).
Regarding independent claim 31, Suh discloses a memory system (Fig. 1), comprising:
memory cells configured to store and provide access to content data (see page 3, par. 0033-0034);
a plurality of mode registers (MRs) (Fig. 1: 180-1-180-M) communicatively coupled to the memory cells (see page 3, par. 0033-0034) and configured to store control data associated with operations of the memory cells (see page 6, par. 0059);
an external communication interface (Fig. 1: 130) coupled to the memory cells (see page 3, par. 0033-0034) and the plurality of MRs (Fig. 1: 180-1-180-M), the external communication interface configured to facilitate external communications for the storage to and the access of the content data (see page 3, par. 0028); and
a control circuit (Fig. 1: 160) coupled to the functional circuitry, the plurality of MRs, and the external communication interface, the logic configured to:
receive one grouped MR command through the external communication interface (see page 6, par. 0062); and
in response to the one grouped MR command, access the plurality of MRs (see page 6, par. 0062).
Regarding claim 32, Suh discloses wherein:
the one grouped MR command is configured to access the control data from the plurality of MRs;
the control circuit is configured to read the control data from the plurality of MRs in response to the group read command; and
the external communication interface is configured to send the control data externally in response to the one grouped MR command (see page 6, par. 0059).
Regarding claim 34, Suh discloses wherein:
the one grouped MR command is for storing the control data in the plurality of the MRs;
the communication circuit is configured to receive the control data along with the one grouped MR command; and
the control circuit is configured to store the control data across the plurality of mode registers in response to the one grouped MR command (see page 6, par. 0059).
Regarding claim 39, Suh discloses wherein the memory system is a Dynamic Random Access Memory (DRAM) (see page 3, par. 0027); and
the external communication interface includes a data (DQ) interface, wherein the one group-access command is received through the DQ interface (Fig. 1: DQ, see also page 3, par. 0027).
Regarding independent claim 40, Suh discloses a method of operating an apparatus, the method comprising:
receiving a single-access command from an external controller (see page 6, par. 0059), wherein the single- access command is configured to access one mode register (MR) within a plurality of MRs that is configured to control operations of functional circuitry within the apparatus (see page 6, par. 0059);
in response to the single-access command, access the one MR in the plurality of MRs (see page 6, par. 0059);
receiving one grouped access command that is configured to store control data at a plurality of mode registers (MRs) or read the control data from the plurality of MRs (see page 6, par. 0062); and
in response to the one grouped MR command, accessing the plurality of MRs (see page 6, par. 0062).
Allowable Subject Matter
Claims 23, 25-29, 33 and 35-38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 23, there is no teaching or suggestion in the prior art of record to provide the recited plurality of MRs includes two or more subgroups of MRs, wherein each of the two or more subgroups include two or more MRs; the one group-access command is a group read command that further includes an identifier indicating one of the two or more subgroups; the logic is configured to read a portion of the control data from the two or more MRs in the indicated one of the two or more subgroups; and the communication circuit is configured to send the portion of the control data externally in response to the group read command.
With respect to claim 25, there is no teaching or suggestion in the prior art of record to provide the recited logic is configured to receive and response to the one group-access command after completing a training operation.
With respect to claim 27, there is no teaching or suggestion in the prior art of record to provide the recited functional circuitry is configured to operate at a first speed, in responding to the group write command, the logic is configured to operate at a second speed that is slower than the first speed when the group write command is received before completing the training operation.
With respect to claim 29, there is no teaching or suggestion in the prior art of record to provide the recited plurality of MRs includes two or more subgroups of MRs, wherein each of the two or more subgroups include two or more MRs; the one group-access command is a group write command that further includes an identifier indicating one of the two or more subgroups; the communication circuit is configured to receive a portion of the control data along with the group write command; and the logic is configured to store the portion of the control data to the two or more MRs in the indicated one of the two or more subgroups.
With respect to claim 33, there is no teaching or suggestion in the prior art of record to provide the recited plurality of MRs includes two or more subgroups of MRs, wherein each of the two or more subgroups include two or more MRs; the one grouped MR command is for reading one subgroup from the two or more subgroups of MRs; the control circuit is configured to read a portion of the control data from the two or more MRs in the one subgroup of the two or more subgroups; and the communication circuit is configured to send the portion of the control data externally in response to the one grouped MR command.
With respect to claim 35, there is no teaching or suggestion in the prior art of record to provide the recited control circuit is configured to receive and respond to the one group MR command after completing a training operation.
With respect to claim 37, there is no teaching or suggestion in the prior art of record to provide the recited control circuit is configured to: the memory cells are configured to operate at to a first speed; in responding to the one grouped MR command, the control circuit is configured to operate at a second speed that is slower than the first speed when the grouped MR command is received before completing the training operation.
With respect to claim 38, there is no teaching or suggestion in the prior art of record to provide the recited control circuit is configured to: determine a configuration and a burst length associated with the one grouped MR; and access the plurality of MRs according to the configuration and the burst length.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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