DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin, TW 201409627 A.
Claim 1: Lin discloses a wiring board (“The invention relates to a package structure of a wafer and a carrier board”, technical-field) with a multi-layer structure having a plurality of build-up layers (20, 30, 16, 22, FIG. 3), wherein,
among the build-up layers, a build-up layer (16+24) on a front surface side formed last has a first solder pad and a second solder pad,
a solder resist layer (22) is provided on the front surface side of the build-up layer on a front surface side,
and heights of the first solder pad and the second solder pad from front surfaces thereof to a front surface of the solder resist layer are different from each other (FIG. 3).
PNG
media_image1.png
305
541
media_image1.png
Greyscale
Claim 2: the solder resist layer includes opening portions through which the front surface of the first solder pad and the front surface of the second solder pad are exposed to the front surface side, and the front surface of the solder resist layer excluding the opening portions has an approximately uniform height (FIG. 3).
Claim 3: the build-up layer on the front surface side further includes a third solder pad, and the first solder pad, the second solder pad, and the third solder pad are formed at equal intervals.
PNG
media_image2.png
259
560
media_image2.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Guo, CN 108028233 A. Lin does not disclose that the first solder pad and the second solder pad include solder balls having approximately a same diameter and approximately a same shape on the front surface side – solder balls are not illustrated on the shorter wiring pads 16. However, it was known in the art to have conductors of different heights with the same size solder ball on the end of each. See Guo, FIG. 4, solder balls 188. It would have been obvious to have used the same size solder balls in Lin as common in the art and known for conductors of different heights.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Guo, or alternatively over Lin in view of Guo and Choi, US 2023/0352411 A1. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Guo and Choi.
Claim 5 recites that the first solder pad and the second solder pad are formed such that a difference between the heights is determined by heights of semiconductor chips to be bonded to the front surface side of the solder balls. This is a statement of intended use. The semiconductor chips are not recited, and the board of Lin is capable of being attached to chips of various heights. Alternatively, Choi FIG. 1, [0038], discloses that the tops of the chip 120 and the chip package 150 are coplanar, but the bottom of the chip 120 is lower. It would have been obvious in light of Lin to bridge that difference with contacts of different heights.
Claim 7: Lin in view of Guo and Choi has the wiring board according to claim 5; and the semiconductor chips (50).
Claim 6 recites that the first solder pad and the second solder pad are formed such that a difference between the heights is determined by heights of mounting pad portions of the semiconductor chips to be bonded to the front surface side of the solder balls. This is a statement of intended use; the chips are not part of the recited invention, and the device of Lin is capable of being attached to chips as recited in claim 6. Alternatively, in Lin in view of Choi, a difference between the heights would be determined by heights of mounting pad portions of the semiconductor chips to be bonded to the front surface side of the solder balls
PNG
media_image3.png
314
676
media_image3.png
Greyscale
Claim 8: Lin in view of Guo and Choi discloses the wiring board according to claim 6; the semiconductor chips; and the mounting pad portions.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kato, US 2011/0284277 A1. Lin discloses:
among a plurality of build-up layers, a build-up layer on a front surface side formed last has a first solder pad (16) and a second solder pad (16+24),
a solder resist layer (22) is provided on the front surface side of the build-up layer on a front surface side,
and heights of the first solder pad and the second solder pad from front surfaces thereof to a front surface of the solder resist layer are different from each other (FIG. 3).
Lin does not disclose the claimed method for forming the structure, but it was known in the art. See Kato, which discloses
a step of forming a wiring layer (24), the first solder pad (60), and the second solder pad (60) in the build-up layer on the front surface side;
a step of forming a plating resist layer (154) such that a part of the front surface of the first solder pad and a part of the front surface of the second solder pad are exposed to the front surface side (FIG. 5(D));
a step of depositing copper on the front surface side of the first solder pad and the second solder pad by a copper plating treatment (FIG. 6(A), [0068]);
a step of stripping the plating resist layer (FIG. 6(B), [0069]);
a step of forming the solder resist layer on the front surface side of the build-up layer on the front surface side; and a step of providing, in the solder resist layer, opening portions (71) through which a part of the front surface of the first solder pad and a part of the front surface of the second solder pad are exposed to the front surface side (FIG. 6(C)m [0073]).
It would have been obvious to have used a known method to form a device such as that of Lin.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER BRADFORD/Primary Examiner, Art Unit 2897
Prosecution Insights