DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of applicant’s Amendment, filed 07 September 2026. The changes and remarks disclosed therein have been considered.
No claims have been cancelled/added by Amendment. Therefore, claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 07/09/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S Patent No. 12,165,710 B2 (‘710). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘710claims.
US Patent No. 12,165,710
US Patent Application No. 2025/0046381 A1
1. A memory device comprising: a sense amplifier (SA) latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively connected to the sense node, the dynamic latch comprising: a latch transistor having a source coupled to a source bias node and a drain selectively connected to the sense node; and one or more set transistors coupled between the SA latch and a gate of the latch transistor, the one or more set transistors also selectively connected to the sense node; a sense line comprising the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line that is coupled to a string of series-connected memory cells; and control logic coupled to at least the SA latch and the dynamic latch, the control logic to perform operations comprising: causing a pre-program verify voltage to provide a boost to the sense node; and in response to detecting a high bit value stored in the SA latch, causing a set voltage to turn on the one or more set transistors so that one of a first bias voltage or a second bias voltage is stored at the latch transistor, wherein: the first bias voltage is useable for slow programming of a selected memory cell of the string of series-connected memory cells; and the second bias voltage is useable for fast programming of the selected memory cell of the string of series-connected memory cells, wherein the fast programming is faster than the slow programming.
2. The memory device of claim 1, wherein the first bias voltage is higher than the second bias voltage, and wherein the pre-program verify voltage comprises one of a first pre-program verify voltage applied when storing the first bias voltage at the latch transistor or a second pre-program verify voltage applied when storing the second bias voltage at the latch transistor, the first pre-program verify voltage being lower than the second pre-program verify voltage.
3. The memory device of claim 2, wherein the first pre-program verify voltage is approximately half the second pre-program verify voltage.
4. The memory device of claim 1, wherein the first bias voltage is associated with a slow selective slow program convergence voltage and is programmed at a level of a common collector voltage (Vcc), and wherein the set voltage is greater than Vcc plus a threshold voltage of the one or more set transistors.
5. The memory device of claim 4, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the first bias voltage to the sense node, the operations further comprise: applying a trigger voltage to the SA latch and to the source bias node; and turning on the enable transistor so the first bias voltage, stored at the latch transistor, is applied to the sense node.
6. The memory device of claim 4, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the first bias voltage to the sense node, the operations further comprise: applying a trigger voltage to the source bias node; applying a local voltage source supply (VSSL) voltage to the SA latch; and turning on the enable transistor so the first bias voltage, stored at the latch transistor, is applied to the sense node.
7. The memory device of claim 1, wherein the second bias voltage is associated with a fast selective slow program convergence voltage and is programmed at a level of a common collector voltage (Vcc) less a threshold voltage of the latch transistor, and wherein the set voltage is approximately the pre-program verify voltage plus a threshold voltage of the one or more set transistors.
8. The memory device of claim 7, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the second bias voltage to the sense node, the operations further comprise: applying a ground voltage to the SA latch and to the source bias node; and turning on the enable transistor so the second bias voltage, stored at the latch transistor, is applied to the sense node.
9. The memory device of claim 7, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the second bias voltage to the sense node, the operations further comprise: applying a ground voltage to the source bias node; applying a local voltage source supply (VSSL) voltage to the SA latch; and turning on the enable transistor so the second bias voltage, stored at the latch transistor, is applied to the sense node.
10. The memory device of claim 1, further comprising a data elaborator coupled to the SA latch, wherein the operations further comprise: causing the sense node to be coupled to ground; and in response to detecting the high bit value stored in the SA latch, causing a program verify pass voltage to be transferred to the data elaborator.
11. A method of operating a memory device comprising a sense amplifier (SA) latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively connected to the sense node, the dynamic latch including a latch transistor and one or more set transistors; a sense line comprising the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line that is coupled to a string of series-connected memory cells, and wherein the method of operating the memory device comprises performing a plurality of operations comprising: causing a pre-program verify voltage to provide a boost to the sense node; and in response to detecting a high bit value stored in the SA latch, causing a set voltage to turn on the one or more set transistors of the dynamic latch so that one of a first bias voltage or a second bias voltage is stored at the latch transistor, wherein: the first bias voltage is useable for slow programming of a selected memory cell of the string of series-connected memory cells; and the second bias voltage is useable for fast programming of the selected memory cell of the string of series-connected memory cells, wherein the fast programming is faster than the slow programming.
12. The method of claim 11, wherein the first bias voltage is higher than the second bias voltage, and wherein the pre-program verify voltage comprises one of a first pre-program verify voltage useable for storing the first bias voltage at the latch transistor or a second pre-program verify voltage useable for storing the second bias voltage at the latch transistor, the first pre-program verify voltage being lower than the second pre-program verify voltage.
13. A memory device comprising: a sense amplifier (SA) latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively connected to the sense node; a sense line comprising the sense node and selectively connected to the SA latch, the dynamic latch, and a bit line, wherein the bit line is coupled to a string of series-connected memory cells; and control logic coupled to the SA latch and the dynamic latch, wherein to program a bit line bias, the control logic is to perform operations comprising: causing a program pulse to be sent down the bit line to program a selected memory cell of the string of series-connected memory cells; causing an output voltage of the SA latch to be sent to the sense node, wherein the output voltage of the SA latch is a common collector voltage (Vcc); causing a first voltage of the sense node to be selectively discharged by the dynamic latch to generate an updated first voltage at the sense node; and causing a bit value stored in the SA latch to be selectively flipped depending on a value of the updated first voltage of the sense node.
14. The memory device of claim 13, wherein the dynamic latch comprises: an enable transistor connected in series with a latch transistor, the latch transistor having a source coupled to a source bias node and the enable transistor having a drain selectively connected to the sense node; and one or more set transistors coupled between the drain of the enable transistor and a gate of the latch transistor; and wherein causing the first voltage of the sense node to be selectively discharged by a second voltage of the dynamic latch comprises: applying a trigger voltage to the SA latch and to the source bias node; and turning on the enable transistor to selectively discharge the updated first voltage at the sense node via the dynamic latch.
15. The memory device of claim 13, further comprising: a bit line clamp transistor coupled between the sense line and the bit line; an enable transistor coupled between the bit line clamp transistor and a first regulator voltage; and a second bit line clamp transistor coupled between the bit line clamp transistor and a second regulator voltage; and wherein the operations further comprise: turning off the second bit line clamp transistor; moving a voltage of a gate of the bit line clamp transistor to a clamp voltage; and turning on the enable transistor to send the first regulator voltage to the sense line as a pre-voltage level for a selective slow program convergence voltage.
16. The memory device of claim 15, wherein the clamp voltage comprises a difference between a slow selective slow program convergence voltage and a fast selective slow program convergence voltage.
17. The memory device of claim 15, further comprising: a lower bias transistor coupled between the bit line clamp transistor and the first regulator voltage; an upper bias transistor coupled between the second bit line clamp transistor and the second regulator voltage; and a bit line precharge transistor coupled between gates of the lower and upper bias transistors and the SA latch; and wherein the operations further comprise: keeping the second bit line clamp transistor turned off; and turning off the bit line precharge transistor.
18. The memory device of claim 17, wherein the dynamic latch comprises: an enable transistor connected in series with a latch transistor, the latch transistor having a source coupled to a source bias node and the enable transistor having a drain selectively connected to the sense node; and one or more set transistors coupled between the drain of the enable transistor and a gate of the latch transistor; and wherein the operations further comprise: applying a ground voltage to the source bias node; asserting multiple control signals of the SA latch to enable updating the output voltage of the SA latch; and turning on the enable transistor so that the output voltage of the SA latch is selectively discharged depending on the bias voltage stored in the latch transistor.
19. The memory device of claim 17, further comprising: an isolation transistor connected to the sense line and coupled between the bit line clamp transistor and the dynamic latch; and wherein the operations further comprise: keeping the second bit line clamp transistor turned off; keeping the bit line precharge transistor turned off; applying the Vcc to a source bias node of the dynamic latch; triggering the SA latch to release a bias voltage used for fast programming of the selected memory cell; and causing the isolation transistor to clamp the bias voltage.
20. The memory device of claim 19, wherein the operations further comprise: causing the bit line clamp transistor to increase a clamp voltage that is applied to a gate of the bit line clamp transistor, wherein the increased clamp voltage comprises a slow selective slow program convergence voltage plus a threshold voltage of the isolation transistor; and causing the lower bias transistor to be turned on to pass the first regulator voltage to the bit line clamp transistor.
1. A memory device comprising: a sense amplifier (SA) latch selectively connected to a sense node; a dynamic latch connected to the SA latch and selectively coupled to the sense node, the dynamic latch comprising: a latch transistor having a source coupled to a source bias node and a drain selectively coupled to the sense node; and one or more set transistors coupled between the SA latch and a gate of the latch transistor, the one or more set transistors also selectively coupled to the sense node; and control logic coupled to at least the SA latch and the dynamic latch, the control logic to perform operations comprising: causing a pre-program verify voltage to provide a boost to the sense node; and in response to detecting a high bit value stored in the SA latch, causing a set voltage to turn on the one or more set transistors so that one of a first bias voltage or a second bias voltage is stored at the latch transistor.
2. The memory device of claim 1, wherein the first bias voltage is higher than the second bias voltage, and wherein the pre-program verify voltage comprises one of a first pre-program verify voltage applied when storing the first bias voltage at the latch transistor or a second pre-program verify voltage applied when storing the second bias voltage at the latch transistor, the first pre-program verify voltage being lower than the second pre-program verify voltage.
3. The memory device of claim 2, wherein the first pre-program verify voltage is approximately half the second pre-program verify voltage.
4. The memory device of claim 1, wherein the first bias voltage is associated with a slow selective slow program convergence voltage and is programmed at a level of a common collector voltage (Vcc), and wherein the set voltage is greater than Vcc plus a threshold voltage of the one or more set transistors.
5. The memory device of claim 4, further comprising a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line that is coupled to a string of memory cells, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the first bias voltage to the sense node, the operations further comprise: applying a trigger voltage to the SA latch and to the source bias node; and turning on the enable transistor so the first bias voltage, stored at the latch transistor, is applied to the sense node.
6. The memory device of claim 4, further comprising a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line that is coupled to a string of memory cells, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the first bias voltage to the sense node, the operations further comprise: applying a trigger voltage to the source bias node; applying a local voltage source supply (VSSL) voltage to the SA latch; and turning on the enable transistor so the first bias voltage, stored at the latch transistor, is applied to the sense node.
7. The memory device of claim 1, wherein the second bias voltage is associated with a fast selective slow program convergence voltage and is programmed at a level of a common collector voltage (Vcc) less a threshold voltage of the latch transistor, and wherein the set voltage is approximately the pre-program verify voltage plus a threshold voltage of the one or more set transistors.
8. The memory device of claim 7, further comprising a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line that is coupled to a string of memory cells, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the second bias voltage to the sense node, the operations further comprise: applying a ground voltage to the SA latch and to the source bias node; and turning on the enable transistor so the second bias voltage, stored at the latch transistor, is applied to the sense node.
9. The memory device of claim 7, further comprising a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line that is coupled to a string of memory cells, wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the second bias voltage to the sense node, the operations further comprise: applying a ground voltage to the source bias node; applying a local voltage source supply (VSSL) voltage to the SA latch; and turning on the enable transistor so the second bias voltage, stored at the latch transistor, is applied to the sense node.
10. The memory device of claim 1, further comprising a data elaborator coupled to the SA latch, wherein the operations further comprise: causing the sense node to be coupled to ground; and in response to detecting the high bit value stored in the SA latch, causing a program verify pass voltage to be transferred to the data elaborator.
11. A memory device comprising: a sense amplifier (SA) latch selectively coupled to a sense node; a dynamic latch coupled to the SA latch and selectively coupled to the sense node; a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line, wherein the bit line is coupled to a string of memory cells; and control logic coupled to the SA latch and the dynamic latch, wherein to program a bit line bias, the control logic is configured to: cause a program pulse to be sent down the bit line to program a selected memory cell of the string of memory cells; cause an output voltage of the SA latch to be sent to the sense node; cause a voltage of the sense node to be selectively discharged by the dynamic latch to generate an updated voltage at the sense node; and cause a bit value stored in the SA latch to be selectively flipped depending on a value of the updated voltage of the sense node.
12. The memory device of claim 11, wherein the dynamic latch comprises: an enable transistor coupled in series with a latch transistor, the latch transistor having a source coupled to a source bias node and the enable transistor having a drain selectively coupled to the sense node; and one or more set transistors coupled between the drain of the enable transistor and a gate of the latch transistor; and wherein, to cause the voltage of the sense node to be selectively discharged by a second voltage of the dynamic latch, the control logic is to: apply a trigger voltage to the SA latch and to the source bias node; and turn on the enable transistor to selectively discharge the updated voltage at the sense node via the dynamic latch.
13. The memory device of claim 11, further comprising: a bit line clamp transistor coupled between the sense line and the bit line; an enable transistor coupled between the bit line clamp transistor and a first regulator voltage; and a second bit line clamp transistor coupled between the bit line clamp transistor and a second regulator voltage; and wherein the control logic is further configured to: turn off the second bit line clamp transistor; move a voltage of a gate of the bit line clamp transistor to a clamp voltage; and turn on the enable transistor to send the first regulator voltage to the sense line as a pre-voltage level for a selective slow program convergence voltage.
14. The memory device of claim 13, wherein the clamp voltage comprises a difference between a slow selective slow program convergence voltage and a fast selective slow program convergence voltage.
15. The memory device of claim 13, further comprising: a lower bias transistor coupled between the bit line clamp transistor and the first regulator voltage; an upper bias transistor coupled between the second bit line clamp transistor and the second regulator voltage; and a bit line precharge transistor coupled between gates of the lower and upper bias transistors and the SA latch; and wherein the control logic is further configured to: keep the second bit line clamp transistor turned off; and turn off the bit line precharge transistor.
16. A memory device comprising: a page buffer comprising: a sense amplifier (SA) latch selectively coupled to a sense node; and a dynamic latch coupled to the SA latch and selectively coupled to the sense node, wherein the dynamic latch comprises: an enable transistor coupled in series with a latch transistor, the latch transistor having a source coupled to a source bias node and the enable transistor having a drain selectively coupled to the sense node; and one or more set transistors coupled between the drain of the enable transistor and a gate of the latch transistor; and control logic coupled to the page buffer, wherein, to generate an updated voltage at the sense node, the control logic is to perform operations comprising causing a voltage of the sense node to be selectively discharged by the dynamic latch, wherein the causing comprises: causing a trigger voltage to be applied to the SA latch and the source bias node; and turning on the enable transistor to selectively discharge the updated voltage at the sense node via the dynamic latch.
17. The memory device of claim 16, wherein the sense node is coupled to a bit line, and wherein to program a bit line bias, the operations further comprise: causing a program pulse to be sent down the bit line to program a selected memory cell; causing an output voltage of the SA latch to be sent to the sense node; causing the updated voltage to be generated at the sense node; and causing a bit value stored in the SA latch to be selectively flipped depending on a value of the updated voltage of the sense node.
18. The memory device of claim 16, wherein the page buffer further comprises: a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line; a bit line clamp transistor coupled between the sense line and the bit line; an enable transistor coupled between the bit line clamp transistor and a first regulator voltage; and a second bit line clamp transistor coupled between the bit line clamp transistor and a second regulator voltage; and wherein the operations further comprise: turning off the second bit line clamp transistor; moving a voltage of a gate of the bit line clamp transistor to a clamp voltage; and turning on the enable transistor to send the first regulator voltage to the sense line as a pre-voltage level for a selective slow program convergence voltage.
19. The memory device of claim 18, wherein the clamp voltage comprises a difference between a slow selective slow program convergence voltage and a fast selective slow program convergence voltage.
20. The memory device of claim 16, wherein the operations further comprise: causing a pre-program verify voltage to provide a boost to the sense node; and in response to detecting a high bit value stored in the SA latch, causing a set voltage to turn on the one or more set transistors so that one of a first bias voltage or a second bias voltage is stored at the latch transistor.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-20’s “control logic” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Li et al (US 9,922,719 B2 hereinafter “Li”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Li, for example in Figs. 1-7B, discloses a memory device (e.g., memory device 598; in Fig. 5A related in Figs. 1-4, 6-7) comprising:
a sense amplifier (SA) latch (e.g., having a power supply for a sense amplifier; in Fig. 6A related in Figs. 1-5, 7) selectively connected to a sense node (e.g., a node coupled to SEN line; in Fig. 6C related in Figs. 1-5, 7);
a dynamic latch (e.g., dynamic latch 622; in Fig. 6C related in Figs. 1-5, 7) connected to the SA latch and selectively coupled to the sense node (see for example in Fig. 6C related in Figs. 1-5, 7), the dynamic latch comprising:
a latch transistor (e.g., transistors in 622; in Fig. 6C related in Figs. 1-5, 7) having a source coupled to a source bias node (e.g., a transistor with INV having a source connected to ground; in Fig. 6C related in Figs. 1-5, 7) and a drain selectively coupled to the sense node (via the other transistors to SEN; in Fig. 6c); and
one or more set transistors (e.g., transistor 627; in Fig. 6C related in Figs. 1-5, 7) coupled between the SA latch and a gate of the latch transistor (e.g., INV to a gate of the transistor in 622; in Fig. 6C related in Figs. 1-5, 7), the one or more set transistors also selectively coupled to the sense node (via DSET in 622; in Fig. 6C related in Figs. 1-5, 7); and control logic (e.g., CONTROL CIRCUITRY 510; in Figs. 5A, 6C related in Figs. 1-4, 7) coupled to at least the SA latch and the dynamic latch (see for example in Figs. 5-6 related in Figs. 1-47), the control logic to perform operations comprising:
causing a pre-program verify voltage to provide a boost to the sense node (via on chip charge pump system; in Fig. 5A related in Figs. 1-4, 6-7); and
in response to detecting a high bit value stored in the SA latch (via sense amplifier’s function; in Figs. 6A-6C related in Figs. 1-5, 7), causing a set voltage to turn on the one or more set transistors so that one of a first bias voltage or a second bias voltage is stored at the latch transistor (via the transistors in 622; in Fig. 6C related in Figs. 1-5, 7).
The structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, Li, for example in Figs.1-7, discloses wherein the first bias voltage is higher than the second bias voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), and wherein the pre-program verify voltage comprises one of a first pre-program verify voltage applied when storing the first bias voltage at the latch transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above) or a second pre-program verify voltage applied when storing the second bias voltage at the latch transistor, the first pre-program verify voltage being lower than the second pre-program verify voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, Li, for example in Figs. 1-7, discloses wherein the first pre-program verify voltage is approximately half the second pre-program verify voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, Li, for example in Figs. 1-7, discloses wherein the first bias voltage is associated with a slow selective slow program convergence voltage and is programmed at a level of a common collector voltage (Vcc) (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), and wherein the set voltage is greater than Vcc plus a threshold voltage of the one or more set transistors (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, Li, for example in Figs. 1-7, discloses further comprising a sense line comprising the sense node and selectively coupled to the SA latch (e.g., SEN line; in Fig. 6C related in Figs. 1-5, 7, as discussed above), the dynamic latch, and a bit line that is coupled to a string of memory cells (via BL; in Fig. 6C related in Figs. 1-5, 7), wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line (via the transistors with DSET; in Fig. 6C related in Figs. 1-5, 7, as discussed above), and wherein, to apply the first bias voltage to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), the operations further comprise: applying a trigger voltage to the SA latch and to the source bias node; and turning on the enable transistor so the first bias voltage, stored at the latch transistor, is applied to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, Li, for example in Figs. 1-7, discloses further comprising a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line that is coupled to a string of memory cells (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line, and wherein, to apply the first bias voltage to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), the operations further comprise: applying a trigger voltage to the source bias node; applying a local voltage source supply (VSSL) voltage to the SA latch; and turning on the enable transistor so the first bias voltage, stored at the latch transistor, is applied to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, Li, for example in Figs. 1-7, discloses wherein the second bias voltage is associated with a fast selective slow program convergence voltage and is programmed at a level of a common collector voltage (Vcc) less a threshold voltage of the latch transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), and wherein the set voltage is approximately the pre-program verify voltage plus a threshold voltage of the one or more set transistors (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, Li, for example in Figs. 1-7, discloses further comprising a sense line (via SEN line; in Fig. 6C related in Figs 1-5, 7) comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line that is coupled to a string of memory cells (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), and wherein, to apply the second bias voltage to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), the operations further comprise: applying a ground voltage to the SA latch and to the source bias node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and turning on the enable transistor so the second bias voltage, stored at the latch transistor, is applied to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 9, Li, for example in Figs. 1-7, discloses further comprising a sense line comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line that is coupled to a string of memory cells (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), wherein the dynamic latch further comprises an enable transistor coupled between the latch transistor and the sense line (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), and wherein, to apply the second bias voltage to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), the operations further comprise: applying a ground voltage to the source bias node; applying a local voltage source supply (VSSL) voltage to the SA latch (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and turning on the enable transistor so the second bias voltage, stored at the latch transistor, is applied to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, Li, for example in Figs. 1-7, discloses further comprising a data elaborator coupled to the SA latch, wherein the operations further comprise: causing the sense node to be coupled to ground (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and in response to detecting the high bit value stored in the SA latch, causing a program verify pass voltage to be transferred to the data elaborator (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 11, Li, for example in Figs. 1-7, discloses a memory device (e.g., memory device 598; in Fig. 5A related in Figs. 1-4, 6-7) comprising:
a sense amplifier (SA) latch (e.g., having a power supply for a sense amplifier; in Fig. 6A related in Figs. 1-5, 7) selectively coupled to a sense node (e.g., a node coupled to SEN line; in Fig. 6C related in Figs. 1-5, 7);
a dynamic latch connected to the SA latch and selectively coupled to the sense node (e.g., dynamic latch 622; in Fig. 6C related in Figs. 1-5, 7, as discussed above);
a sense line comprising the sense node and selectively coupled to the SA latch (e.g., SEN line; in Fig. 6C related in Figs. 1-5, 7), the dynamic latch, and a bit line (e.g., BL; in Fig. 6C related in Figs. 1-5, 7), wherein the bit line is coupled to a string of memory cells (e.g., NAND string; in Fig. 6A related in Figs. 1-5, 7); and
control logic (e.g., CONTROL CIRCUITRY 510; in Figs. 5A, 6C related in Figs. 1-4, 7) coupled to the SA latch and the dynamic latch, wherein to program a bit line bias (see for example in Figs. 5A, 6C related in Figs. 1-4, 7), the control logic is configured to:
cause a program pulse to be sent down the bit line to program a selected memory cell of the string of memory cells (implied for program operation; in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above);
cause an output voltage of the SA latch to be sent to the sense node; cause a voltage of the sense node to be selectively discharged by the dynamic latch to generate an updated voltage at the sense node (via the transistors in 622; in Fig. 6C related in Figs. 1-5, 7); and cause a bit value stored in the SA latch to be selectively flipped depending on a value of the updated voltage of the sense node (via sense amplifier’s function; in Figs. 6A-6C related in Figs. 1-5, 7).
The structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, Li, for example in Figs. 1-7, discloses wherein the dynamic latch comprises: an enable transistor coupled in series with a latch transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), the latch transistor having a source coupled to a source bias node and the enable transistor having a drain selectively coupled to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7); and one or more set transistors coupled between the drain of the enable transistor and a gate of the latch transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7); and wherein, to cause the voltage of the sense node to be selectively discharged by a second voltage of the dynamic latch, the control logic is to: apply a trigger voltage to the SA latch and to the source bias node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7); and turn on the enable transistor to selectively discharge the updated voltage at the sense node via the dynamic latch (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, Li, for example in Figs. 1-7, discloses further comprising: a bit line clamp transistor coupled between the sense line and the bit line (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); an enable transistor coupled between the bit line clamp transistor and a first regulator voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and a second bit line clamp transistor coupled between the bit line clamp transistor and a second regulator voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and wherein the control logic is further configured to: turn off the second bit line clamp transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); move a voltage of a gate of the bit line clamp transistor to a clamp voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and turn on the enable transistor to send the first regulator voltage to the sense line as a pre-voltage level for a selective slow program convergence voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, Li, for example in Figs. 1-7, discloses wherein the clamp voltage comprises a difference between a slow selective slow program convergence voltage and a fast selective slow program convergence voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 15, Li, for example in Figs. 1-7, discloses further comprising: a lower bias transistor coupled between the bit line clamp transistor and the first regulator voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); an upper bias transistor coupled between the second bit line clamp transistor and the second regulator voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and a bit line precharge transistor coupled between gates of the lower and upper bias transistors and the SA latch (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and wherein the control logic is further configured to: keep the second bit line clamp transistor turned off; and turn off the bit line precharge transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 16, Li, for example in Figs. 1-7, discloses a memory device (e.g., memory device 598; in Fig. 5A related in Figs. 1-4, 6-7) comprising:
a page buffer (within READ/WRITE CIRCUITS 565; in Fig. 5A) comprising:
a sense amplifier (SA) latch (e.g., having a power supply for a sense amplifier; in Fig. 6A related in Figs. 1-5, 7) selectively coupled to a sense node (e.g., a node coupled to SEN line; in Fig. 6C related in Figs. 1-5, 7); and
a dynamic latch coupled to the SA latch and selectively coupled to the sense node (e.g., dynamic latch 622; in Fig. 6C related in Figs. 1-5, 7, as discussed above), wherein the dynamic latch comprises:
an enable transistor (e.g., gate of a transistor with no label; in Fig. 6C related in Figs. 1-5, 7) coupled in series with a latch transistor (e.g., the transistors in 622; in Fig. 6C related in Figs. 1-5, 7), the latch transistor having a source coupled to a source bias node (e.g., a transistor with INV having a source connected to ground; in Fig. 6C related in Figs. 1-5, 7) and the enable transistor having a drain selectively coupled to the sense node (via the other transistors to SEN; in Fig. 6C related in Figs. 1-5, 7); and
one or more set transistors (e.g., the transistors in 622; in Fig. 6C related in Figs. 1-5, 7) coupled between the drain of the enable transistor and a gate of the latch transistor (see for example in Fig. 6C related in Figs. 1-5, 7); and control logic (e.g., CONTROL CIRCUITRY 510; in Figs. 5A, 6C related in Figs. 1-4, 7) coupled to the page buffer, wherein, to generate an updated voltage at the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), the control logic is to perform operations comprising causing a voltage of the sense node to be selectively discharged by the dynamic latch (via the transistors in 622; in Fig. 6C related in Figs. 1-5, 7), wherein the causing comprises: causing a trigger voltage to be applied to the SA latch and the source bias node (via sense amplifier’s function; in Figs. 6A-6C related in Figs. 1-5, 7); and turning on the enable transistor to selectively discharge the updated voltage at the sense node via the dynamic latch (via the transistors in 622; in Fig. 6C related in Figs. 1-5, 7).
The structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 17, Li, for example in Figs. 1-7, discloses wherein the sense node is coupled to a bit line (e.g., BL; in Fig. 6C related in Figs. 1-5, 7, as discussed above), and wherein to program a bit line bias (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), the operations further comprise: causing a program pulse to be sent down the bit line to program a selected memory cell (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); causing an output voltage of the SA latch to be sent to the sense node; causing the updated voltage to be generated at the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and causing a bit value stored in the SA latch to be selectively flipped depending on a value of the updated voltage of the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 18, Li, for example in Figs. 1-7, discloses wherein the page buffer further comprises: a sense line (e.g., SEN line; in Figs. 6C related in Figs. 1-5, 7) comprising the sense node and selectively coupled to the SA latch, the dynamic latch, and a bit line (e.g., BL; in Fig. 6C related in Figs. 1-5, 7); a bit line clamp transistor coupled between the sense line and the bit line; an enable transistor coupled between the bit line clamp transistor and a first regulator voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and a second bit line clamp transistor coupled between the bit line clamp transistor and a second regulator voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and wherein the operations further comprise: turning off the second bit line clamp transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); moving a voltage of a gate of the bit line clamp transistor to a clamp voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and turning on the enable transistor to send the first regulator voltage to the sense line as a pre-voltage level for a selective slow program convergence voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 19, Li, for example in Figs. 1-7, discloses wherein the clamp voltage comprises a difference between a slow selective slow program convergence voltage and a fast selective slow program convergence voltage (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 20, Li, for example in Figs. 1-7, discloses wherein the operations further comprise: causing a pre-program verify voltage to provide a boost to the sense node (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above); and in response to detecting a high bit value stored in the SA latch (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above), causing a set voltage to turn on the one or more set transistors so that one of a first bias voltage or a second bias voltage is stored at the latch transistor (see for example in Figs. 5A, 6C related in Figs. 1-4, 7, as discussed above). Also, the structure in of the prior art (Li) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 II A).
Response to Arguments
Applicant's arguments filed 09 July 2026 have been fully considered but they are not persuasive.
Applicant argues “claim 1 expressly requires that the control logic detect…”, as recited in claim 1 as same as claims 11, 16 (remarks file 09 July 2026, the second paragraph on pages 11-12).
In response the reference of Li (US 9,922,719 B2) discloses control circuitry 510 to control the sense amplifier having two-inverter (as called latch) connected to cross over together in Fig. 6.
Applicant argues that the reference of Li (US 9,922,719 B2) discloses no “SA latch capable of storing a bit value”, as recited in claim 1 as same as claims 11, 16 (see remarks file 09 July 2026, the second paragraph on pages 11-12).
In response “SA latch” is a label only and does not structurally distinguish over sense amplifier latch of Li (see Fig. 6C below).
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Applicant argues that the reference of Li (US 9,922,719 B2) does not disclose set transistors “coupled between the SA latch and a gate of the latch transistor”, as recited in claim 1, as same as claims 11, 16 (see remarks file 09 July 2026, third paragraph on pages 11-12).
In response the transistors within dynamic latch 622; in Fig. 6C, coupled between the SA latch and a gate (INV) of the latch transistor.
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 09/09/2026
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