DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mari Curbelo et al. (US 2015/0035585).
Regarding claim 1, Mari Curbelo discloses a method [e.g. figs.4 (or 3), 9/7], comprising: detecting [e.g. the sense circuit 902/702 also, see para. 0046] a load voltage in response to a cross-conduction current flowing through a first transistor and a second transistor [e.g. 402, 404]; in response to detecting the load voltage, determining [e.g. 902s] whether one of the first transistor or the second transistor triggered the cross-conduction current; and in response to determining that the first transistor triggered the cross-conduction current, increasing a first delay of a first rising edge of a first gate voltage to be applied to the first transistor [e.g. add an interlock/dead time, para. 0027]; and in response to determining that the second transistor triggered the cross-conduction current, increasing a second delay of a second rising edge of a second gate voltage to be applied to the second transistor [e.g. add an interlock/dead time, para. 0027].
Regarding claim 3, Mari Curbelo discloses the method of claim 1, wherein increasing at least one of the first delay or the second delay comprises: generating [e.g. 906, 316/706, 316] a control voltage in response to the load voltage; mapping [e.g. 707/314] the control voltage to at least one of the first delay or the second delay; and delaying [e.g. 707/314] at least one of the first rising edge or the second rising edge responsive to at least one of the first delay or the second delay.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mari Curbelo et al. (US 2015/0035585) in view of Wickersham et al. (US 7,741,881).
Regarding claim 4, Mari Curbelo discloses the method of claim 1. Mari Curbelo discloses a switch device that is an inverter, not a buck converter. However, a boost voltage converter, a buck voltage converter, or a buck-boost voltage converter is a well-known switch device. It would be obvious for a person having ordinary skills in the art to modify detecting method of Mari Curbelo and apply to a converter. For example, Wickersham discloses a buck converter [see fig. 1/2/3]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Mari Curbelo in accordance with the teaching of Wickersham regarding a converter in order to provide improvement for controlling the dead time.
Claims 5, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mari Curbelo et al. (US 2015/0035585) in view of Barnes (US 6,420,909).
Regarding claim 5, Mari Curbelo discloses the method of claim 1, wherein the detecting the load voltage includes using a cross detector circuit [e.g. the sense circuit 902/702] except that includes a third transistor and a fourth transistor. Mari Curbelo does not explicitly disclose comparator 904/704 of the cross detector circuit includes a third transistor and a fourth transistor. However, it’s well-known that a comparator comprising FET transistors. For example, US 6,420,909 by Barnes discloses a comparator [e.g. fig. 4/5] comprising FET transistors.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Mari Curbelo in accordance with the teaching of Barnes regarding a comparator in order to provide the detail of a comparator.
Regarding claim 7, the combination discussed above discloses the method of claim 5, wherein detecting the load voltage includes coupling a third transistor [e.g. 56/58 0r 40/46 Barnes] to a load [see. the phase out fig. 4/3 Mari Curbelo], and measuring a current based on a voltage generated by the load.
Regarding claim 10, the combination discussed above discloses the method of claim 5, wherein the third transistor and the fourth transistor are each N-Channel field effect transistors (NFETs) [e.g. 52, 54 fig. 5/30, 32 fig. 4 Barnes].
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mari Curbelo et al. (US 2015/0035585) in view of Thompson et al. (US 2014/0300329).
Regarding claim 8, the combination discussed above discloses the method of claim 1, except wherein at least one of the first delay or the second delay is provided by a counter or a resistor-capacitor network. However, it’s well-known to provide a delay by using a counter. For example, Thompson discloses to provide a delay by using a counter [see at least abstract, para. 0010]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Mari Curbelo in accordance with the teaching of Thompson regarding a counter in order to provide a delay by using a well-known counter.
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mari Curbelo et al. (US 2015/0035585) in view of Kawagishi et al. (US 8,058,854).
Regarding claim 9, the combination discussed above discloses the method of claim 1, except wherein the first transistor and the second transistor are each N-Channel field effect transistors (NFETs). However, it’s well-known to replace a p-type transistor with n-type transistor, and vice versa. For example, Kawagishi discloses to replace a p-type transistor with n-type transistor, and vice versa [Col. 4, lines 49-51]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Mari Curbelo in accordance with the teaching of Kawagishi regarding a transistor in order to provide a simple substitution of one known element for another to obtain predictable results.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mari Curbelo et al. (US 2015/0035585) in view of Barnes (US 6,420,909) and Thompson et al. (US 2014/0300329).
Regarding claim 11, the combination discussed above discloses the method of claim 10, wherein the first transistor is coupled to a load [see. the phase out fig. 4/3 Mari Curbelo]. The combination does not disclose the first transistor and the second transistor are FET transistors. However, it’s well known to utilize FET transistors. For example, Thompson discloses to utilize MOSFETs as a first transistor and a second transistor [e.g. 508, 518 fig, 5], such that the new combination discloses a drain of the first transistor is coupled to a load [see. the phase out fig. 4/3 Mari Curbelo], and a source of the first transistor is coupled to a drain of the second transistor. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Mari Curbelo and Barnes in accordance with the teaching of Thompson regarding MOSFETs in order to utilize well-known FETs as the switching transistors.
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mari Curbelo et al. (US 2015/0035585) in view of Barnes (US 6,420,909) and Sato et al. (US 2018/006250).
Regarding claim 11, the combination discussed above discloses the method of claim 10, wherein the first transistor is coupled to a load [see. the phase out fig. 4/3 Mari Curbelo]. The combination does not disclose the first transistor and the second transistor are FET transistors. However, it’s well known to utilize FET transistors. For example, Sato discloses to utilize MOSFETs as a first transistor and a second transistor [e.g. Q1, Q2 fig, 1; 402, 404 fig. 7, paras. 0018, 0045], such that the new combination discloses a drain of the first transistor is coupled to a load [see. the phase out fig. 4/3 Mari Curbelo], and a source of the first transistor is coupled to a drain of the second transistor. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Mari Curbelo and Barnes in accordance with the teaching of Sato regarding MOSFETs in order to utilize well-known FETs as the switching transistors.
Regarding claim 12, the combination discussed above discloses the method of claim 11, wherein a gate of the first transistor is coupled to a gate of the third transistor, a gate of the second transistor is coupled to a gate of the fourth transistor, and a source of the third transistor is coupled to a drain of the fourth transistor [see transistors 702s, 703s fig. 7, to provide parallel switching].
Claims 1-5, 7-8 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thompson et al. (US 2014/0300329) in view of Mari Curbelo et al. (US 2015/0035585).
Regarding claim 1, Thompson discloses a method [e.g. fig. 5], comprising: detecting [e.g. 540/550] a load voltage in response to a cross-conduction current flowing through a first transistor [e.g. 518] and a second transistor [e.g. 508]; in response to detecting the load voltage, determining [e.g. 540, 550] whether one of the first transistor or the second transistor triggered the cross-conduction current; and in response to determining that the first transistor triggered the cross-conduction current, increasing a first delay of a first rising edge of a first gate voltage to be applied to the first transistor [e.g. add a dead time; see at least paras. 0045-0047]; and in response to determining that the second transistor triggered the cross-conduction current, increasing a second delay of a second rising edge of a second gate voltage to be applied to the second transistor. Thompson discloses to detect the output signal of 568, Thompson does not disclose to detect the output signal of 566. However, Mari Curbelo discloses to detect on both high-side and low-side switches, such that the combination discloses in response to determining that the second transistor triggered the cross-conduction current, increasing a second delay of a second rising edge of a second gate voltage to be applied to the second transistor. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Thompson in accordance with the teaching of Mari Curbelo regarding a switch device in order to control switches based on the detected signal, respectively.
Regarding claim 2, the combination discussed above discloses the method of claim 1, further comprising in response to not detecting the load voltage [e.g. it’s not below threshold. Thompson only compares the detected value to a threshold], reducing the first delay and the second delay [see para. 0054 Thompson].
Regarding claim 3, the combination discussed above discloses the method of claim 1, wherein increasing at least one of the first delay or the second delay comprises: generating a control voltage in response to the load voltage [e.g. 540, 550 Thompson. Note: the combination also detect he output signal of 566]; mapping [e.g. 560 Thompson] the control voltage to at least one of the first delay or the second delay; and delaying [e.g. 560] at least one of the first rising edge or the second rising edge responsive to at least one of the first delay or the second delay.
Regarding claim 4, the combination discussed above discloses the method of claim 1, further comprising operating a converter based on at least one of the first gate voltage or the second gate voltage, the converter including at least one of a boost voltage converter, a buck voltage converter, or a buck-boost voltage converter [see at least abstract Thompson].
Regarding claim 5, the combination discussed above discloses the method of claim 1, wherein the detecting the load voltage includes using a cross detector circuit [e.g. 540/550 Thompson] that includes a third transistor and a fourth transistor [see the two N-type FET current mirror transistors on the left side (between label 602 and label 630 fig. 6) Thompson].
Regarding claim 7, the combination discussed above discloses the method of claim 12, wherein detecting the load voltage includes coupling a third transistor [ see the left transistor of the two N-type FET current mirror transistors on the left side (between label 602 and label 630] to a load [see. Vout Thompson], and measuring a current based on a voltage generated by the load.
Regarding claim 8, the combination discussed above discloses the method of claim 1, wherein at least one of the first delay or the second delay is provided by a counter [see at least abstract Thompson] or a resistor-capacitor network.
Regarding claim 10, the combination discussed above discloses the method of claim 5, wherein the third transistor and the fourth transistor are each N-Channel field effect transistors (NFETs) [see the two N-type FET current mirror transistors on the left side (between label 602 and label 630].
Regarding claim 11, the combination discussed above discloses the method of claim 10, wherein a drain of the first transistor is coupled to a load [see Vout, para. 0009 Thompson], and a source of the first transistor is coupled to a drain of the second transistor.
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thompson et al. (US 2014/0300329) in view of Mari Curbelo et al. (US 2015/0035585) and Kawagishi et al. (US 8,058,854).
Regarding claim 9, the combination discussed above discloses the method of claim 1, except wherein the first transistor and the second transistor are each N-Channel field effect transistors (NFETs). However, it’s well-known to replace a p-type transistor with n-type transistor, and vice versa. For example, Kawagishi discloses to replace a p-type transistor with n-type transistor, and vice versa [Col. 4, lines 49-51]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Thompson and Mari Curbelo in accordance with the teaching of Kawagishi regarding a transistor in order to provide a simple substitution of one known element for another to obtain predictable results.
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thompson et al. (US 2014/0300329) in view of Mari Curbelo et al. (US 2015/0035585), and Sato et al. (US 2018/0062501).
Regarding claim 12, the combination discussed above discloses the method of claim 11, except wherein a gate of the first transistor is coupled to a gate of the third transistor, a gate of the second transistor is coupled to a gate of the fourth transistor, and a source of the third transistor is coupled to a drain of the fourth transistor. However, Sato discloses parallel switching device [ see 702, 704 fig, 7], such that the combination discloses a gate of the first transistor is coupled to a gate of the third transistor, a gate of the second transistor is coupled to a gate of the fourth transistor, and a source of the third transistor is coupled to a drain of the fourth transistor. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Thompson, and Mari Curbelo in accordance with the teaching of Sato regarding a switching device in order to provide parallel driving.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/PATRICK C CHEN/Primary Examiner, Art Unit 2842