Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2024 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1, 7 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 8 and 14 of U.S. Patent No.12154640 respectively. Although the claims at issue are not identical, they are not patentably distinct from each other because
The apparatus/method of claim 1, 7 and 14 in the present application are anticipated by the respective apparatus/method in claim 1, 8 and 14 respectively in US Patent 12154640. The limitations addressed in the apparatus are entirely contained within the respective apparatus in claim 1, 8 and 14 n US Patent 12154640 as shown below table.
Therefore one of ordinary skill in the art before the effective filing data of the claimed invention would have been able to use the claimed invention of US Patent 12154640 to achieve the claimed invention of the present application presented below in the table.
This is a non-provisional nonstatutory double patenting rejection because the patentably indistinct claims have been patented.
18924615 (PRESENT)
12154640 (17/856,827)
1. A method, comprising:
determining a memory device includes a first portion of memory cells that are invalid;
performing, in response to determining the first portion of memory cells are invalid, a predetermined pattern program operation on a second portion of memory cells of the memory device without erasing the first portion of memory cells, wherein performing the predetermined pattern program operation includes programming a predetermined pattern to the second portion of memory cells; and
erasing the first portion of memory cells and the second portion of memory cells.
1. A method, comprising:
completing a first processing stage on a memory device from a plurality of processing stages, wherein the plurality of processing stages utilize corresponding predetermined pattern program operations;
determining a first portion of memory cells of the memory device are invalid from the first processing stage;
starting a second processing stage;
programing, during the second processing stage, a predetermined pattern on a second portion of memory cells of the memory device based on the second processing stage in response to determining the first portion of the memory cells are invalid and prior to erasing the first portion of memory cells of the memory device that are determined to be invalid from the first processing stage; and
erasing, during the second processing stage, the predetermined pattern from the second portion of memory cells in response to programming the predetermined pattern on the second portion of memory cells.
7. A method, comprising:
programming a memory device with user data at a first portion of memory cells;
determining the memory device includes invalid user data at the first portion of memory cells;
performing, in response to determining the first portion of memory cells include invalid user data, a predetermined pattern program operation on a second portion of memory cells of the memory device without erasing the invalid user data, wherein performing the predetermined pattern program operation includes programming a predetermined pattern to the second portion of memory cells; and
erasing the first portion of memory cells and the second portion of memory cells as a memory block of the memory device.
8. A method, comprising:
completing a first processing stage on a memory device from a plurality of processing stages, wherein the plurality of processing stages utilize corresponding plurality of predetermined patterns;
determining a first portion of memory cells of the memory device are invalid from the first processing stage;
programming, during a second processing stage, a predetermined pattern on a second portion of memory cells from the plurality of the plurality of predetermined patterns on the memory device in response to completing the first processing stage of the memory device and prior to erasing the first portion of memory cells of the memory device that are determined to be invalid from the first processing stage, wherein the predetermined pattern is based on the processing stage of the memory device; and
erasing, during the second processing stage, the predetermined pattern from the second portion of memory cells of the memory device in response to programming the predetermined pattern on the memory device.
14. An apparatus, comprising:
a memory device; and
a controller couplable to the memory device, wherein the controller is configured to:
perform a predetermined pattern program operation on a first portion of memory cells of the memory device, wherein performing the predetermined pattern program operation includes programming a predetermined pattern to the first portion of memory cells;
program the memory device with user data to a second portion of memory cells of the memory device;
determine the memory device includes invalid user data at the second portion of memory cells; and
erase the first portion of memory cells and the second portion of memory cells as a memory block of the memory device.
14. An apparatus, comprising:
a memory device; and
a controller couplable to the memory device, wherein the controller is configured to:
perform a first type of processing stage on the memory device from a plurality of types of processing stages;
determine a first portion of memory cells of the memory device that are invalid from the first type of processing stage;
perform a second type of processing stage on the memory device from the plurality of types of processing stages;
program, during the second type of processing stage, a predetermined pattern to at least a second portion of the memory device to a predetermined program state based on the second type of the processing stage of completed on the memory device and prior to erasing the first portion of memory cells of the memory device that are determined to be invalid from the first processing stage; and
erase, during the second type of processing stage, the predetermined pattern from the second portion of the memory device in response to programming the predetermined pattern to at least the second portion of the memory device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teoh et al., US 20220115074, hereinafter Teoh, in view of Yuzurihara et al. 20120198292, hereinafter Yuzurihara.
As per claim 1, Teoh teaches A method, comprising:
determining a memory device (FIG.2, [0032] SSD 187) includes a first portion of memory cells that are invalid; (Fig 2, [0032]: NAND block 210 in NAND flash non-volatile memory device 208; Fig. 6, [0049] if the number of read errors does not fall within the maximum acceptable read error threshold in step 610......;)
performing, in response to determining the first portion of memory cells are invalid, a predetermined pattern program operation on a second portion of memory cells of the memory device without erasing the first portion of memory cells, wherein performing the predetermined pattern program operation includes programming a predetermined pattern to the second portion of memory cells; and (Fig. 6, [0049]; Fig 2,[0040], the memory cells 360 of at least one designated calibration wordline 350 of NAND block 210 may be programmed with a pre-defined data pattern. [0013])
EXCEPT
erasing the first portion of memory cells and the second portion of memory cells.
Yuzurihara teaches
erasing the first portion of memory cells and the second portion of memory cells. ( [0049] Next, the testing section 230 instructs the memory under test 10 to erase the memory of the memory under test 10; Fig. 2, [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Teoh to incorporate the teaching of the elements from Yuzurihara as indicated above, in order to get rid of unwanted data from memory after testing and thereby allowing the memory to have lower storage capacity. (Yuruzihara [0025])
As per claim 7, Teoh teaches A method, comprising:
programming a memory device with user data at a first portion of memory cells; (Fig 2, [0040]; [0013])
determining the memory device includes invalid user data at the first portion of memory cells; (Fig 2, [0032]: NAND block 210 in NAND flash non-volatile memory device 208; Fig. 6, [0049] if the number of read errors does not fall within the maximum acceptable read error threshold in step 610......;)
performing, in response to determining the first portion of memory cells include invalid user data, a predetermined pattern program operation on a second portion of memory cells of the memory device without erasing the invalid user data, wherein performing the predetermined pattern program operation includes programming a predetermined pattern to the second portion of memory cells; and
(Fig. 6, [0049]; Fig 2,[0040], the memory cells 360 of at least one designated calibration wordline 350 of NAND block 210 may be programmed with a pre-defined data pattern. [0013])
EXCEPT
erasing the first portion of memory cells and the second portion of memory cells as a memory block of the memory device.
Yuzurihara teaches
erasing the first portion of memory cells and the second portion of memory cells as a memory block of the memory device.
( [0049] Next, the testing section 230 instructs the memory under test 10 to erase the memory of the memory under test 10; Fig. 2, [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Teoh to incorporate the teaching of the elements from Yuzurihara as indicated above, in order to get rid of unwanted data from memory after testing and thereby allowing the memory to have lower storage capacity. (Yuruzihara [0025])
As per claim 14, Teoh teaches An apparatus, comprising:
a memory device (FIG.2, [0032] SSD 187); and
a controller couplable to the memory device, (Fig. 2, a SSD flash memory controller 206) wherein the controller is configured to:
perform a predetermined pattern program operation on a first portion of memory cells of the memory device, wherein performing the predetermined pattern program operation includes programming a predetermined pattern to the first portion of memory cells; (Fig. 6, [0049]; Fig 2,[0040], the memory cells 360 of at least one designated calibration wordline 350 of NAND block 210 may be programmed with a pre-defined data pattern. [0013])
program the memory device with user data to a second portion of memory cells of the memory device;
determine the memory device includes invalid user data at the second portion of memory cells; and
(Fig 2, [0032]: NAND block 210 in NAND flash non-volatile memory device 208; Fig. 6, [0049] if the number of read errors does not fall within the maximum acceptable read error threshold in step 610......;)
EXCEPT
erase the first portion of memory cells and the second portion of memory cells as a memory block of the memory device.
Yuzurihara teaches
erase the first portion of memory cells and the second portion of memory cells as a memory block of the memory device.
( [0049] Next, the testing section 230 instructs the memory under test 10 to erase the memory of the memory under test 10; Fig. 2, [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Teoh to incorporate the teaching of the elements from Yuzurihara as indicated above, in order to get rid of unwanted data from memory after testing and thereby allowing the memory to have lower storage capacity. (Yuruzihara [0025])
As per claim 2, Teoh-Yuzurihara The method as applied above in claim 1, Teoh further teaches wherein the predetermined pattern program operation is performed during a user operation of the memory device. (Fig 2, [0040]; [0013]; [0012])
As per claim 10, Teoh-Yuzurihara The method as applied above in claim 7, Teoh further teaches wherein the predetermined pattern program operation is performed during a user operation of the memory device. (Fig 2, [0040]; [0013]; [0012])
As per claim 3, Teoh-Yuzurihara The method as applied above in claim 1, Teoh further teaches wherein programming the predetermined pattern includes programming the second portion of memory cells of the memory device to a predetermined program state. (Fig 2, [0040])
As per claim 12, Teoh-Yuzurihara The method as applied above in claim 7, Teoh further teaches wherein the predetermined pattern is a predetermined pattern of program states for the second portion of memory cells. (Fig 2, [0040])
As per claim 4, Teoh-Yuzurihara The method as applied above in claim 1, Teoh further teaches wherein the first portion of memory cells and the second portion of memory cells comprise an entire block of memory cells of the memory device.
([0013] …...then calculate a new and corrected read compare voltage magnitude (Vr_1) by subtracting the same voltage shift magnitude (Vsh) from the default Vr level, and then may use the corrected Vr_1 to read data with a reduced RBER value from the entire given SSD NAND block, and see Fig 4: ∆Vr)
As per claim 5, Teoh-Yuzurihara The method as applied above in claim 1, Teoh further teaches wherein programming the predetermined pattern reduces threshold voltage shift in the first portion and the second portion of the memory device after erasing the first portion and the second portion of the memory device. (Fig 2, [0040]; [0013])
As per claim 6, Teoh-Yuzurihara The method as applied above in claim 1, Teoh further teaches wherein programming the predetermined pattern increases a read window budget (RWB) of the memory device after erasing the first portion and the second portion of the memory device. (Fig 4: ∆Vr, [0043]; [0013])
As per claim 8, Teoh-Yuzurihara The method as applied above in claim 7, Teoh further teaches wherein the predetermined pattern is based on environmental conditions of the memory device. (Fig 2, [0040]; [0013]; [0012])
As per claim 20, Teoh-YuzuriharaThe apparatus as applied above in claim 14, Teoh further teaches wherein the predetermined pattern is based on environmental conditions of the memory device. (Fig 2, [0040]; [0013]; [0012])
As per claim 9, Teoh-Yuzurihara The method as applied above in claim 7, Teoh further teaches wherein the predetermined pattern is based on a workload of the memory device. (Fig 2, par. [0040];. [0013]; [0012])
As per claim 19, Teoh-YuzuriharaThe apparatus as applied above in claim 14, Teoh further teaches wherein the predetermined pattern is based on a workload of the memory device. (Fig 2, par. [0040];. [0013]; [0012])
As per claim 11, Teoh-Yuzurihara The method as applied above in claim 10, Teoh further teaches wherein the predetermined pattern is programmed on non-erased portions of the memory device. (Fig 2, [0040])
As per claim 15, Teoh-YuzuriharaThe apparatus as applied above in claim 14, Teoh further teaches wherein the controller is configured to program the predetermined pattern on non-erased portions of the memory device. (Fig 2, [0040]
As per claim 13, Teoh-Yuzurihara The method as applied above in claim 7, Teoh further teaches wherein erasing the first portion of memory cells and the second portion of memory cells is performed prior to reading the second portion of memory cells. (Fig 2, [0040] the memory cells 360 of at least one designated calibration wordline 350 of NAND block 210 may be programmed with a pre-defined data pattern. SSD controller 206 may erase data from the remaining memory cells 360 of the other (non-calibration) wordlines of NAND block 210 that are different from the designated calibration wordline in response to erase commands received by SSD controller 206 from host programmable integrated circuit 155).
As per claim 16, Teoh-YuzuriharaThe apparatus as applied above in claim 14, Teoh further teaches wherein the controller is configured to program the predetermined pattern on non-written portions of the memory device.
(Fig 2, [0040] the memory cells 360 of at least one designated calibration wordline 350 of NAND block 210 may be programmed with a pre-defined data pattern.)
As per claim 17, Teoh-YuzuriharaThe apparatus as applied above in claim 14, Teoh further teaches wherein the controller is configured to program the predetermined pattern prior to erasing the first portion of the memory cells of the memory device. (Fig 2, [0040] the memory cells 360 of at least one designated calibration wordline 350 of NAND block 210 may be programmed with a pre-defined data pattern. SSD controller 206 may erase data from the remaining memory cells 360 of the other (non-calibration) wordlines of NAND block 210 that are different from the designated calibration wordline in response to erase commands received by SSD controller 206 from host programmable integrated circuit 155).
As per claim 18, Teoh-YuzuriharaThe apparatus as applied above in claim 14, Teoh further teaches wherein the controller is configured to program the predetermined pattern prior to programming the first portion of the memory cells of the memory device.
(Fig 2, [0040] the memory cells 360 of at least one designated calibration wordline 350 of NAND block 210 may be programmed with a pre-defined data pattern. SSD controller 206 may erase data from the remaining memory cells 360 of the other (non-calibration) wordlines of NAND block 210 that are different from the designated calibration wordline in response to erase commands received by SSD controller 206 from host programmable integrated circuit 155).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Querbach et al., US 20150187439, INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR
Sun et al., US 20160125951, DETECTING VOLTAGE THRESHOLD DRIFT
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111