DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 3–7, 10–14, 17–21 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 , 3-8, 10-15, 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Halbert et al., US 2017/0060681 A1 (“Halbert”) and further in view of Cai et al. (“Errors in Flash-Memory-Based Solid-State Drives”).
Claim 1: Halbert teaches a method, comprising:
transmitting, to a dynamic random access memory (DRAM) device, one or more commands associated with a scrub operation of the DRAM device (e.g., Halbert teaches that a memory controller sends a trigger for ECS mode – either an ECS command (Fig. 4A, ¶[0040]-[0042]) or a mode register setting (Fig. 4B, ¶[0069]) – which causes the DRAM to perform internal read-correct-writeback cycles, i.e., scrubbing (¶[0025], ¶[0054])); and
polling, by a host device coupled with the DRAM device and based at least in part on transmitting the one or more commands, a register at the DRAM device (e.g., After ECS operations, the host (memory controller) reads error information from multipurpose registers (MPRs) such as MPR Page 4 (address of row with max errors, Fig. 4C) and MPR Page 5 (segment count, Fig. 4D). This constitutes polling because the host actively retrieves the register contents (¶[0027], ¶[0071]-[0074])), wherein the register of the DRAM device indicates a quantity of errors resulting from the scrub operation (e.g., Halbert’s MPRs store explicit error quantities: • Segment count – number of rows having N or more errors (Fig. 4D, EC[19:0]; ¶[0073]) • Maximum count – maximum number of errors in any row (Fig. 4C, EC[5:0]; ¶[0071]) Thus, the register directly indicates a numeric error quantity derived from the scrub).
Not explicitly taught by Halbert is that the quantity of errors resulting from the scrub operation is within a range of three or more ranges tracked by the DRAM device. However, Cai describes using multiple thresholds to define different error severity levels, such as in multi-rate ECC (Section 4.7) where the raw bit error rate (RBER) falls into one of several ranges, each triggering a different ECC engine. Similarly, Cai discusses soft decoding levels in LDPC (Section 5.2.2) where the error rate is classified into multiple bins to determine decoding effort. These teachings establish that tracking error quantities in three or more ranges was routine in memory reliability engineering. Therefore, before the effective filing date of the claimed invention, it would have been obvious to modify Halbert’s DRAM to categorize the error count from a scrub operation into three or more ranges (e.g., 0 errors, 1-2 errors, ≥3 errors) and to have the register indicate which range the quantity falls into in order to improve error reporting granularity.
As per claims 8 and 15, the claimed features are rejected similarly to claim 1 above.
Claim 3: Halbert and Cai et al teach the method of claim 1, further comprising: transmitting one or more write commands to the DRAM device, wherein the one or more write commands comprise data to be written to one or more rows of the DRAM device (e.g. Cai: Host writes data to SSD via write commands (Section 1.3.1, pp. 5–6); Data is written in pages (rows) (Section 1.1, p. 4). Thus, performing write operations in conjunction with scrub operations is inherent in Cai’s refresh and garbage collection processes, which involve reading and rewriting data. Also Halbert’s ECS mode includes a Write command that writes corrected data back to the DRAM array (¶[0054]; Table 4).
As per claims 10 and 17, the claimed features are rejected similarly to claim 3 above.
Claim 4: Halbert and Cai et al teach the method of claim 1, further comprising: transmitting, to the DRAM device, a set of commands for accessing one or more rows of the DRAM device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations (e.g. Cai: Refresh operations involve accessing rows (wordlines) to read and reprogram data (Section 4.3, pp. 32–34) ) and commands for accessing rows are inherent in flash operations (Section 2.3, pp. 15–16. Halbert’s ECS sequence includes ACT (activate), RD (read), WR (write), PRE (precharge) – a set of commands that access specific rows (¶[0051], Fig. 4A). The scrub operation is expressly associated with these commands).
As per claims 11 and 18, the claimed features are rejected similarly to claim 4 above.
Claim 5: Halbert and Cai et al teach the method of claim 4, wherein the set of commands are associated with one or more refresh operations (Section 4.3, pp. 32–34) ) and commands for accessing rows are inherent in flash operations (Section 2.3, pp. 15–16). And Halbert teaches that ECS mode can be triggered in conjunction with refresh commands (e.g., REFab) and that the scrubbing process is independent but can be coordinated with refresh timing (¶[0022], ¶[0051]).
As per claims 12 and 19, the claimed features are rejected similarly to claim 5 above.
Claim 6: Halbert and Cai et al teach he method of claim 1, wherein transmitting, to the DRAM device, an indication of a rate for one or more scrub operations, wherein polling the register at the DRAM device is based at least in part on transmitting the indication of the rate (e.g Halbert’s memory controller controls the rate of scrubbing by issuing ECS commands periodically or setting mode register bits (¶[0082]-[0083]). The host can thus transmit an indication of the rate (e.g., by commanding ECS at specific intervals)).
As per claims 13 and 20, the claimed features are rejected similarly to claim 6 above.
Claim 7: Halbert and Cai et al teach the method of claim 1, but fail to teach that the range of the three or more ranges indicates an integrity of data stored at the DRAM device (e.g., Halbert’s registers directly indicate data integrity – e.g., the segment count (number of rows with N or more errors) is a direct measure of the overall health of the DRAM (¶[0073]).
As per claims 14 and 21, the claimed features are rejected similarly to claim 7 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 6/2/2026
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