DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 10/23/2024. Claims 1-21 are presented for examination and have been considered below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-30 of U.S. Patent No. 11,169,730 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every limitation claimed in the present application is anticipated by the claimed invention of U.S. Patent No. 11,169,730 B2, as follows:
Present application
US 11,169,730 B2
1. A method, comprising: transmitting, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtaining, by a host device and based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
2. The method of claim 1, wherein obtaining the indicator comprises: polling a register of the memory device to obtain the quantity of errors.
3. The method of claim 1, further comprising: transmitting one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
4. The method of claim 1, further comprising: transmitting, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
5. The method of claim 4, wherein the set of commands are associated with one or more refresh operations.
6. The method of claim 1, further comprising: transmitting, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
7. The method of claim 1, wherein the range of the three or more ranges indicates an integrity of data stored at the memory device.
8. A host device, comprising: at least one interface comprising one or more signal paths operable for communications with at least one memory device; and at least one controller coupled with the at least one interface and configured to cause the host device to: transmit, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtain, by the host device and based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
9. The host device of claim 8, wherein, to obtain the indicator, the at least one controller is configured to cause the host device to: poll a register of the memory device to obtain the quantity of errors.
10. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
11. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
12. The host device of claim 11, wherein the set of commands are associated with one or more refresh operations.
13. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
14. The host device of claim 8, wherein the range of the three or more ranges indicates an integrity of data stored at the memory device.
15. A non-transitory computer-readable medium storing code comprising instructions which, when executed by at least one processor of an electronic device, cause the electronic device to: transmit, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtain, based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
16. The non-transitory computer-readable medium of claim 15, wherein the instructions to obtain the indicator, when executed by the at least one processor of the electronic device, cause the electronic device to: poll a register of the memory device to obtain the quantity of errors.
17. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
19. The non-transitory computer-readable medium of claim 18, wherein the set of commands are associated with one or more refresh operations.
20. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
21. The non-transitory computer-readable medium of claim 15, the range of the three or more ranges indicates an integrity of data stored at the memory device.
1. A method, comprising: performing, at a memory device, a scrub operation comprising reading data and error correction information stored in each row of a plurality of rows of a memory array of the memory device and detecting bit errors in the data of each row based at least in part on the error correction information; monitoring, during the scrub operation, the bit errors detected for the plurality of rows of the scrub operation; determining a quantity of the bit errors detected during the scrub operation based at least in part on the monitoring; determining, from three or more conditions of the memory array each associated with a corresponding level of integrity of data stored at the memory array, a condition of the memory array based at least in part on the quantity of the bit errors detected; and performing, by the memory device, an action associated with the condition of the memory array.
2. The method of claim 1, further comprising: comparing the quantity of the bit errors detected to two or more thresholds, wherein determining the condition of the memory array is based at least in part on the comparing.
3. A method, comprising: performing, at a memory device, a scrub operation comprising reading data and error correction information stored in each row of a plurality of rows of a memory array of the memory device and detecting bit errors in the data of each row based at least in part on the error correction information; monitoring, during the scrub operation, the bit errors detected for the plurality of rows of the scrub operation; determining a quantity of the bit errors detected during the scrub operation based at least in part on the monitoring; determining a difference between the quantity of the bit errors detected during the scrub operation and a second quantity of bit errors detected during a second scrub operation performed before the scrub operation; determining, based at least in part on the quantity of the bit errors detected and the difference, a condition of the memory array; performing, by the memory device, an action associated with the condition of the memory array.
4. A method, comprising: performing, at a memory device, a scrub operation comprising reading data and error correction information stored in each row of a plurality of rows of a memory array of the memory device and detecting bit errors in the data of each row based at least in part on the error correction information; monitoring, during the scrub operation, the bit errors detected for the plurality of rows of the scrub operation; determining a quantity of the bit errors detected during the scrub operation based at least in part on the monitoring; determining a first difference between the quantity of the bit errors detected during the scrub operation and a second quantity of bit errors detected during a second scrub operation performed before the scrub operation; determining a second difference between respective quantities of bit errors detected during scrub operations including at least one scrub operation performed before the second scrub operation; determining a change between the first difference and the second difference; determining, based at least in part on the quantity of the bit errors detected and the change, a condition of the memory array; and performing, by the memory device, an action associated with the condition of the memory array.
5. The method of claim 1, further comprising: storing the error correction information for the plurality of rows of the memory array of the memory device, wherein performing the scrub operation further comprises: comparing the data and the error correction information stored in each row of the plurality of rows of the memory array.
6. The method of claim 1, wherein performing the action comprises transmitting, from the memory device to a host device, an indicator of the condition of the memory array.
7. The method of claim 6, further comprising: receiving, from the host device, a first plurality of scrub commands according to a first rate for scrubbing the memory array, wherein performing the scrub operation is based at least in part on receiving the first plurality of scrub commands; and receiving, from the host device after transmitting the indicator of the condition of the memory array to the host device, a second plurality of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate.
8. The method of claim 7, wherein the second rate is based at least in part on the condition of the memory array.
9. The method of claim 7, wherein the first rate is based at least in part on a voltage, or a temperature, or both associated with the memory array.
10. The method of claim 1, further comprising: determining that the condition of the memory array has changed from a first condition to a second condition associated with a lower integrity of data stored at the memory array than the first condition, wherein determining the condition of the memory array is based at least in part on the determining that the condition of the memory array has changed.
11. The method of claim 10, further comprising: receiving, from a host device, an indication of a first rate for scrubbing the memory array, the first rate associated with the first condition, wherein performing the scrub operation is based at least in part on receiving the indication of the first rate for scrubbing the memory array; determining, at the memory device, a second rate for scrubbing the memory array based at least in part on determining that the condition of the memory array has changed from the first condition to the second condition; and performing a second scrub operation according to the second rate for scrubbing the memory array.
12. The method of claim 10, further comprising: generating, by the memory device, a first plurality of scrub commands for scrubbing the memory array according to a first rate based at least in part on the first condition, wherein performing the scrub operation is based at least in part on generating the first plurality of scrub commands; and generating, by the memory device based at least in part on performing the action associated with the condition of the memory array, a second plurality of scrub commands for scrubbing the memory array according to a second rate that is greater than the first rate.
13. The method of claim 1, further comprising: correcting the bit errors in the data of each row based at least in part on detecting the bit errors in the data of each row.
14. The method of claim 13, wherein performing the scrub operation comprises: receiving, from a host device, a plurality of scrub commands that each correspond to one or more of the plurality of rows of the memory array; performing, for each of the plurality of scrub commands, an error correction operation on the data read from the memory array for the one or more of the plurality of rows to generate second data based at least in part on the error correction information; and writing, for the each of the plurality of scrub commands, the second data to the one or more of the plurality of rows of the memory array.
15. A method, comprising: performing, at a memory device, a scrub operation comprising reading data and error correction information stored in each row of a plurality of rows of a memory array of the memory device, detecting bit errors in the data of each row based at least in part on the error correction information, and correcting the bit errors in the data of each row based at least in part on detecting the bit errors in the data of each row, wherein performing the scrub operation comprises: receiving, from a host device, a plurality of scrub commands that each correspond to one or more of the plurality of rows of the memory array; performing, for each of the plurality of scrub commands, an error correction operation on the data read from the memory array for the one or more of the plurality of rows to generate second data based at least in part on the error correction information; writing, for the each of the plurality of scrub commands, the second data to the one or more of the plurality of rows of the memory array; and performing the reading and the correcting of the bit errors for a first quantity of the plurality of rows of the memory array for each of the plurality of scrub commands; monitoring, during the scrub operation, the bit errors detected for the plurality of rows of the scrub operation; determining a quantity of the bit errors detected during the scrub operation based at least in part on the monitoring; determining, based at least in part on the quantity of the bit errors detected, a condition of the memory array; performing, by the memory device, an action associated with the condition of the memory array; receiving, from the host device, a second plurality of scrub commands after receiving the plurality of scrub commands; and performing, based at least in part on performing the action associated with the condition of the memory array, a second scrub operation comprising reading the data and the error correction information stored in each row of the plurality of rows of the memory array and correcting bit errors in the data of each row based at least in part on the error correction information, wherein performing the second scrub operation comprises performing the reading and the correcting of the bit errors for a second quantity of the plurality of rows of the memory array for each of the second plurality of scrub commands, and wherein the second quantity of the plurality of rows is greater than the first quantity of the plurality of rows.
16. The method of claim 1, further comprising: receiving, from a host device, a set of commands for accessing the memory array; and performing operations indicated by the set of commands for accessing the memory array, wherein performing the scrub operation is based at least in part on performing the operations.
17. A method, comprising: performing, at a memory device, a first set of scrub operations comprising detecting bit errors in a memory array of the memory device according to a first rate for scrubbing the memory array associated with a first condition of the memory array that indicates a first level of integrity of data stored at the memory array; determining a quantity of the bit errors detected during each scrub operation of the first set of scrub operations; determining, from three or more conditions of the memory array each associated with a corresponding of integrity of data stored at the memory array, a second condition of the memory array based at least in part on one or more quantities of the bit errors detected, wherein the second condition of the memory array is associated with a second rate for scrubbing the memory array and indicates a second integrity of data stored at the memory array; and performing a second set of scrub operations comprising detecting bit errors in the memory array according to the second rate for scrubbing the memory array.
18. The method of claim 17, further comprising: transmitting, to a host device, an indicator of the second condition of the memory array.
19. The method of claim 17, further comprising: receiving a first plurality of scrub commands from a host device according to the first rate for scrubbing the memory array, wherein performing the first set of scrub operations according to the first rate is based at least in part on the receiving the first plurality of scrub commands; and receiving a second plurality of scrub commands from the host device according to the second rate for scrubbing the memory array, wherein performing the second set of scrub operations according to the second rate is based at least in part on receiving the second plurality of scrub commands.
20. The method of claim 17, further comprising: receiving, prior to performing the first set of scrub operations, a configuration for performing scrub operations, the configuration indicating the first rate for scrubbing the memory array; and determining the second rate for scrubbing the memory array based at least in part on determining the second condition of the memory array, wherein performing the second set of scrub operations is based at least in part on determining the second rate for scrubbing the memory array.
21. The method of claim 17, wherein: the second condition of the memory array corresponds to a lower level of integrity of data being stored at the memory array than the first condition of the memory array; and the second rate for scrubbing the memory array is greater than the first rate for scrubbing the memory array.
22. The method of claim 17, further comprising: comparing the quantity of the bit errors detected during one of the first set of scrub operations to two or more thresholds, wherein determining the second condition of the memory array is based at least in part on the comparing.
23. The method of claim 17, further comprising: determining a difference between respective quantities of the bit errors detected during a first scrub operation and a second scrub operation of the first set of scrub operations, wherein determining the second condition of the memory array is based at least in part on the difference.
24. The method of claim 17, further comprising: determining a first difference between respective quantities of the bit errors detected during a first subset of the first set of scrub operations; determining a second difference between respective quantities of the bit errors detected during a second subset of the first set of scrub operations including at least one scrub operation performed after the first subset of the first set of scrub operations; and determining a change between the first difference and the second difference, wherein determining the second condition of the memory array is based at least in part on the change.
25. The method of claim 17, further comprising: receiving, from a host device, a plurality of scrub commands that each correspond to a portion of data stored in the memory array; reading, for each of the portions of data, first data and error correction information from the memory array; performing, for the each of the portions of data, an error correction operation on the first data read from the memory array to generate second data, wherein performing the error correction operation is based at least in part on the error correction information; and writing, for the each of the portions of data, the second data to the memory array, wherein performing each of the first set of scrub operations is based at least in part on the writing.
26. An apparatus, comprising: an array of memory cells; and circuitry coupled with the array of memory cells and operable to cause the apparatus to: perform a scrub operation comprising reading data and error correction information stored in each row of a plurality of rows of the array of memory cells and detecting bit errors in the data of each row based at least in part on the error correction information; monitor, during the scrub operation, the bit errors detected for the plurality of rows of the scrub operation; determine a quantity of the bit errors detected during the scrub operation based at least in part on the monitoring; determine, from three or more conditions of the array of memory cells each associated with a corresponding level of integrity of data stored at the array of memory cells, a condition of the array of memory cells based at least in part on the quantity of the bit errors detected; and perform, by the apparatus, an action associated with the condition of the array of memory cells.
27. The apparatus of claim 26, wherein the circuitry is further operable to cause the apparatus to transmit, to a host device, an indicator of the condition of the array of memory cells based at least in part on performing the action associated with the condition of the array of memory cells.
28. The apparatus of claim 27, wherein the circuitry is further operable to cause the apparatus to: receive, from the host device, a first plurality of scrub commands according to a first rate for scrubbing the array of memory cells, wherein performing the scrub operation is based at least in part on receiving the first plurality of scrub commands; and receive, from the host device after transmitting the indicator of the condition of the array of memory cells to the host device, a second plurality of scrub commands according to a second rate for scrubbing the array of memory cells that is greater than the first rate.
29. An apparatus, comprising: an array of memory cells; and circuitry coupled with the array of memory cells and operable to cause the apparatus to: perform a scrub operation comprising reading data and error correction information stored in each row of a plurality of rows of the array of memory cells and detecting bit errors in the data of each row based at least in part on the error correction information; receive, from a host device, a first plurality of scrub commands, wherein performing the scrub operation comprises performing the reading and the detecting of the bit errors for a first quantity of the plurality of rows of the array of memory cells for each of the first plurality of scrub commands; monitor, during the scrub operation, the bit errors detected for the plurality of rows of the scrub operation; determine a quantity of the bit errors detected during the scrub operation based at least in part on the monitoring; determine, based at least in part on the quantity of the bit errors detected, a condition of the array of memory cells; perform, by the apparatus, an action associated with the condition of the array of memory cells; receive, from the host device a second plurality of scrub commands after receiving the first plurality of scrub commands; and perform, based at least in part on performing the action associated with the condition of the array of memory cells, a second scrub operation comprising reading the data and the error correction information stored in each row of the plurality of rows of the array of memory cells and detect bit errors in the data of each row based at least in part on the error correction information, wherein performing the second scrub operation comprises performing the reading and the detecting of the bit errors for a second quantity of the plurality of rows of the array of memory cells for each of the second plurality of scrub commands, and wherein the second quantity of the plurality of rows is greater than the first quantity of the plurality of rows.
30. The apparatus of claim 26, wherein the circuitry is further operable to cause the apparatus to: compare the quantity of the bit errors detected to two or more thresholds, wherein determining the condition of the array of memory cells is based at least in part on the comparing.
Claims 1-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 11,748,021 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every limitation claimed in the present application is anticipated by the claimed invention of U.S. Patent No. 11,748,021, as follows:
Present application
US11,748,021 B2
1. A method, comprising: transmitting, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtaining, by a host device and based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
2. The method of claim 1, wherein obtaining the indicator comprises: polling a register of the memory device to obtain the quantity of errors.
3. The method of claim 1, further comprising: transmitting one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
4. The method of claim 1, further comprising: transmitting, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
5. The method of claim 4, wherein the set of commands are associated with one or more refresh operations.
6. The method of claim 1, further comprising: transmitting, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
7. The method of claim 1, wherein the range of the three or more ranges indicates an integrity of data stored at the memory device.
8. A host device, comprising: at least one interface comprising one or more signal paths operable for communications with at least one memory device; and at least one controller coupled with the at least one interface and configured to cause the host device to: transmit, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtain, by the host device and based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
9. The host device of claim 8, wherein, to obtain the indicator, the at least one controller is configured to cause the host device to: poll a register of the memory device to obtain the quantity of errors.
10. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
11. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
12. The host device of claim 11, wherein the set of commands are associated with one or more refresh operations.
13. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
14. The host device of claim 8, wherein the range of the three or more ranges indicates an integrity of data stored at the memory device.
15. A non-transitory computer-readable medium storing code comprising instructions which, when executed by at least one processor of an electronic device, cause the electronic device to: transmit, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtain, based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
16. The non-transitory computer-readable medium of claim 15, wherein the instructions to obtain the indicator, when executed by the at least one processor of the electronic device, cause the electronic device to: poll a register of the memory device to obtain the quantity of errors.
17. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
19. The non-transitory computer-readable medium of claim 18, wherein the set of commands are associated with one or more refresh operations.
20. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
21. The non-transitory computer-readable medium of claim 15, the range of the three or more ranges indicates an integrity of data stored at the memory device.
1. A method, comprising: receiving, from a host device, a first plurality of scrub commands according to a first rate for scrubbing a memory array of a memory device; performing, at the memory device, a plurality of scrub operations based at least in part on receiving the first plurality of scrub commands; monitoring, during the plurality of scrub operations, one or more bit errors detected for a plurality of rows of the memory array of the memory device for each scrub operation; determining first quantities of bit errors detected during the plurality of scrub operations based at least in part on the monitoring; transmitting, to the host device, an indicator of a condition of the memory array, the condition of the memory array associated with a level of integrity of data stored at the memory array and based at least in part on comparing a first metric associated with the first quantities of the bit errors to a second metric, wherein the first metric corresponds to a first average of the first quantities of bit errors, a change in the first quantities of bit errors, a rate of change of the first quantities of bit errors, or any combination thereof, and wherein the second metric corresponds to a second average of second quantities of bit errors, a second change in the second quantities of bit errors, a second rate of change of the second quantities of bit errors, or any combination thereof; and receiving, from the host device after transmitting the indicator of the condition of the memory array to the host device, a second plurality of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate, wherein the first rate for scrubbing the memory array is based at least in part on one or more first quantities of rows associated with the first plurality of scrub commands, and wherein the second rate for scrubbing the memory array is based at least in part on one or more second quantities of rows associated with the second plurality of scrub commands.
2. The method of claim 1, wherein the plurality of scrub operations comprise reading, for each scrub operation of the plurality of scrub operations, data and error correction information stored in each row of the plurality of rows of the memory array of the memory device and detecting the bit errors in the data of each row based at least in part on the error correction information, the method further comprising: determining, based at least in part on the first quantities of the bit errors detected, the condition of the memory array; wherein transmitting the indicator is based at least in part on determining the condition of the memory array.
3. The method of claim 1, further comprising: determining the first metric associated with the first quantities of bit errors detected during the plurality of scrub operations; and comparing the first metric associated with the first quantities of bit errors to one or more thresholds, the second metric, or both, wherein determining the condition of the memory array is based at least in part on comparing the first metric to the one or more thresholds, the second metric, or both.
4. The method of claim 3, wherein the first metric corresponds to the first average associated with the first quantities of bit errors, a first running average associated with the first quantities of bit errors, a first weighted average of the first quantities of bit errors, or any combination thereof.
5. The method of claim 3, wherein the one or more thresholds for determining the condition of the memory array corresponds to one or more dynamic thresholds, one or more configurable thresholds, or both.
6. The method of claim 3, wherein the second metric corresponds to the second average associated with the second quantities of bit errors, a second running average associated with the second quantities of bit errors, a second weighted average associated with the second quantities of bit errors, or any combination thereof, the second quantities of bit errors detected during a second plurality of scrub operations.
7. The method of claim 1, wherein the second rate is based at least in part on the condition of the memory array.
8. The method of claim 1, wherein the first rate is based at least in part on a voltage associated with the memory array, a temperature associated with the memory array, or both.
9. The method of claim 1, wherein transmitting the indicator of the condition of the memory array comprises transmitting the indicator to the host device via a dedicated condition indicator channel.
10. The method of claim 1, wherein transmitting the indicator of the condition of the memory array comprises outputting the indicator to a register of the memory device, the register operable to be polled by the host device to indicate the indicator.
11. The method of claim 1, wherein the first rate for scrubbing the memory array is based at least in part on a first command reception rate at which the first plurality of scrub commands are received, and wherein the second rate for scrubbing the memory array is based at least in part on a second command reception rate at which the second plurality of scrub commands are received.
12. An apparatus, comprising: a processor; memory coupled with the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to: receive, from a host device, a first plurality of scrub commands according to a first rate for scrubbing a memory array of a memory device; perform, at the memory device, a plurality of scrub operations based at least in part on receiving the first plurality of scrub commands; monitor, during the plurality of scrub operations, one or more bit errors detected for a plurality of rows of the memory array of the memory device for each scrub operation; determine first quantities of bit errors detected during the plurality of scrub operations based at least in part on the monitoring; transmit, to the host device, an indicator of a condition of the memory array, the condition of the memory array associated with a level of integrity of data stored at the memory array and based at least in part on comparing a first metric associated with the first quantities of the bit errors to a second metric, wherein the first metric corresponds to a first average of the first quantities of bit errors, a change in the first quantities of bit errors, a rate of change of the first quantities of bit errors, or any combination thereof, and wherein the second metric corresponds to a second average of second quantities of bit errors, a second change in the second quantities of bit errors, a second rate of change of the second quantities of bit errors, or any combination thereof; and receive, from the host device after transmitting the indicator of the condition of the memory array to the host device, a second plurality of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate, wherein the first rate for scrubbing the memory array is based at least in part on one or more first quantities of rows associated with the first plurality of scrub commands, and wherein the second rate for scrubbing the memory array is based at least in part on one or more second quantities of rows associated with the second plurality of scrub commands.
13. The apparatus of claim 12, wherein the plurality of scrub operations comprise reading, for each scrub operation of the plurality of scrub operations, data and error correction information stored in each row of the plurality of rows of the memory array of the memory device and detecting the bit errors in the data of each row based at least in part on the error correction information, wherein the instructions are further executable by the processor to cause the apparatus to: determine, based at least in part on the first quantities of the bit errors detected, the condition of the memory array; wherein transmitting the indicator is based at least in part on determining the condition of the memory array.
14. The apparatus of claim 12, wherein the instructions are further executable by the processor to cause the apparatus to: determine the first metric associated with the first quantities of bit errors detected during the plurality of scrub operations; and compare the first metric associated with the first quantities of bit errors to one or more thresholds, the second metric, or both, wherein determining the condition of the memory array is based at least in part on comparing the first metric to the one or more thresholds, the second metric, or both.
15. The apparatus of claim 14, wherein the first metric corresponds to the first average associated with the first quantities of bit errors, a first running average associated with the first quantities of bit errors, a first weighted average of the first quantities of bit errors, or any combination thereof.
16. The apparatus of claim 14, wherein the one or more thresholds for determining the condition of the memory array corresponds to one or more dynamic thresholds, one or more configurable thresholds, or both.
17. The apparatus of claim 14, wherein the second metric corresponds to the second average associated with the second quantities of bit errors, a second running average associated with the second quantities of bit errors, a second weighted average associated with the second quantities of bit errors, or any combination thereof, the second quantities of bit errors detected during a previous plurality of scrub operations.
18. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: receive, from a host device, a first plurality of scrub commands according to a first rate for scrubbing a memory array of a memory device; perform, at the memory device, a plurality of scrub operations based at least in part on receiving the first plurality of scrub commands; monitor, during the plurality of scrub operations, one or more bit errors detected for a plurality of rows of the memory array of the memory device for each scrub operation; determine first quantities of bit errors detected during the plurality of scrub operations based at least in part on the monitoring; transmit, to the host device, an indicator of a condition of the memory array, the condition of the memory array associated with a level of integrity of data stored at the memory array and based at least in part on comparing a first metric associated with the first quantities of the bit errors to a second metric, wherein the first metric corresponds to a first average of the first quantities of bit errors, a change in the first quantities of bit errors, a rate of change of the first quantities of bit errors, or any combination thereof, and wherein the second metric corresponds to a second average of second quantities of bit errors, a second change in the second quantities of bit errors, a second rate of change of the second quantities of bit errors, or any combination thereof; and receive, from the host device after transmitting the indicator of the condition of the memory array to the host device, a second plurality of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate, wherein the first rate for scrubbing the memory array is based at least in part on one or more first quantities of rows associated with the first plurality of scrub commands, and wherein the second rate for scrubbing the memory array is based at least in part on one or more second quantities of rows associated with the second plurality of scrub commands.
19. The non-transitory computer-readable medium of claim 18, wherein the plurality of scrub operations comprise reading, for each scrub operation of the plurality of scrub operations, data and error correction information stored in each row of the plurality of rows of the memory array of the memory device and detecting the bit errors in the data of each row based at least in part on the error correction information, wherein the instructions are further executable by the processor to: determine, based at least in part on the first quantities of the bit errors detected, the condition of the memory array; wherein transmitting the indicator is based at least in part on determining the condition of the memory array.
20. The non-transitory computer-readable medium of claim 18, wherein the instructions are further executable by the processor to: determine the first metric associated with the first quantities of bit errors detected during the plurality of scrub operations; and compare the first metric associated with the first quantities of bit errors to one or more thresholds, the second metric, or both, wherein determining the condition of the memory array is based at least in part on comparing the first metric to the one or more thresholds, the second metric, or both.
21. The non-transitory computer-readable medium of claim 18, wherein the first metric corresponds to the first average associated with the first quantities of bit errors, a first running average associated with the first quantities of bit errors, a first weighted average of the first quantities of bit errors, or any combination thereof.
Claims 1-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,141,464 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every limitation claimed in the present application is anticipated by the claimed invention of U.S. Patent No. 12,141,464 B2, as follows:
Present application
US 12,141,464 B2
1. A method, comprising: transmitting, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtaining, by a host device and based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
2. The method of claim 1, wherein obtaining the indicator comprises: polling a register of the memory device to obtain the quantity of errors.
3. The method of claim 1, further comprising: transmitting one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
4. The method of claim 1, further comprising: transmitting, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
5. The method of claim 4, wherein the set of commands are associated with one or more refresh operations.
6. The method of claim 1, further comprising: transmitting, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
7. The method of claim 1, wherein the range of the three or more ranges indicates an integrity of data stored at the memory device.
8. A host device, comprising: at least one interface comprising one or more signal paths operable for communications with at least one memory device; and at least one controller coupled with the at least one interface and configured to cause the host device to: transmit, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtain, by the host device and based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
9. The host device of claim 8, wherein, to obtain the indicator, the at least one controller is configured to cause the host device to: poll a register of the memory device to obtain the quantity of errors.
10. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
11. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
12. The host device of claim 11, wherein the set of commands are associated with one or more refresh operations.
13. The host device of claim 8, wherein the at least one controller is further configured to cause the host device to: transmit, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
14. The host device of claim 8, wherein the range of the three or more ranges indicates an integrity of data stored at the memory device.
15. A non-transitory computer-readable medium storing code comprising instructions which, when executed by at least one processor of an electronic device, cause the electronic device to: transmit, to a memory device, one or more commands associated with a scrub operation of the memory device; and obtain, based at least in part on transmitting the one or more commands, an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors.
16. The non-transitory computer-readable medium of claim 15, wherein the instructions to obtain the indicator, when executed by the at least one processor of the electronic device, cause the electronic device to: poll a register of the memory device to obtain the quantity of errors.
17. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device.
18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations.
19. The non-transitory computer-readable medium of claim 18, wherein the set of commands are associated with one or more refresh operations.
20. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the at least one processor of the electronic device, further cause the electronic device to: transmit, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate.
21. The non-transitory computer-readable medium of claim 15, the range of the three or more ranges indicates an integrity of data stored at the memory device.
1. A method, comprising: performing, at a memory device, a scrub operation comprising reading data stored in one or more rows of the memory device and detecting errors in the data of the one or more rows based at least in part on reading the data; counting a quantity of errors during the scrub operation based at least in part on reading the data stored in the one or more rows and detecting the errors in the data of the one or more rows; comparing the quantity of errors to two or more thresholds associated with three or more ranges, each range of the three or more ranges associated with a respective condition of three or more conditions associated with the memory device; and outputting, by the memory device and based at least in part on the comparing, an indicator of the quantity of errors, the outputting based at least in part on a condition of the three or more conditions and a range of the three or more ranges.
2. The method of claim 1, wherein outputting the indicator comprises: storing the quantity of errors to a register of the memory device.
3. The method of claim 1, wherein outputting the indicator comprises: transmitting, from the memory device to a host device coupled with the memory device, the indicator of the quantity of errors.
4. The method of claim 1, wherein the scrub operation further comprises reading error correction information stored in the one or more rows of the memory device, wherein detecting the errors in the data is based at least in part on reading the error correction information.
5. The method of claim 4, further comprising: correcting the errors detected in the data of the one or more rows based at least in part on reading the data and the error correction information; and writing the error correction information and the data to the one or more rows of the memory device based at least in part on correcting the errors.
6. The method of claim 1, further comprising: receiving one or more write commands from a host device coupled with the memory device, wherein the one or more write commands comprise second data to be written to one or more second rows of the memory device; generating error correction information based at least in part on the second data in the one or more write commands; and writing the error correction information and the second data to one or more second rows of the memory device based at least in part on generating the error correction information.
7. The method of claim 1, further comprising: receiving, from a host device coupled with the memory device, a set of commands for accessing the one or more rows of the memory device; and performing operations indicated by the set of commands for accessing the one or more rows, wherein performing the scrub operation is based at least in part on performing the operations.
8. The method of claim 1, further comprising: determining a difference between the quantity of the errors detected during the scrub operation and a second quantity of errors detected during a second scrub operation performed before the scrub operation, wherein outputting the indicator of the quantity of errors is based at least in part on the difference.
9. The method of claim 1, further comprising: determining a first difference between the quantity of the errors detected during the scrub operation and a second quantity of errors detected during a second scrub operation performed before the scrub operation; determining a second difference between respective quantities of errors detected during scrub operations including at least one scrub operation performed before the second scrub operation; and determining a change between the first difference and the second difference, wherein outputting the indicator of the quantity of errors is based at least in part on the change.
10. The method of claim 9, further comprising: receiving, from a host device coupled with the memory device, an indication of a first rate for scrubbing the one or more rows of the memory device, the first rate associated with the condition, wherein performing the scrub operation is based at least in part on receiving the indication of the first rate for scrubbing the one or more rows of the memory device; determining, at the memory device, a second rate for scrubbing the one or more rows of the memory device based at least in part on determining that the condition of the three or more conditions has changed from the condition to a second condition associated with a lower integrity of data stored at the one or more rows than the condition; and performing a third scrub operation according to the second rate for scrubbing the one or more rows.
11. The method of claim 1, wherein performing the scrub operation comprises: receiving, from a host device coupled with the memory device, a plurality of scrub commands that each correspond to at least one row of the one or more rows of the memory device; performing, for each of the plurality of scrub commands, an error correction operation on the data read from the one or more rows of the memory device for the at least one row to generate second data based at least in part on error correction information; and writing, for each of the plurality of scrub commands, the second data to the at least one row of the one or more rows of the memory device.
12. The method of claim 11, wherein performing the scrub operation comprises: performing the reading and the correcting of the errors for a first quantity of the one or more rows of the memory device for each of the plurality of scrub commands, the method further comprising: receiving, from the host device, a second plurality of scrub commands after receiving a first plurality of scrub commands; and performing, based at least in part on outputting the indicator of the quantity of errors, a second scrub operation comprising reading the data and the error correction information stored in each row of the one or more rows of the memory device and correcting errors in the data of each row based at least in part on the error correction information, wherein performing the second scrub operation comprises performing the reading and the correcting of the errors for a second quantity of the one or more rows of the memory device for each of the second plurality of scrub commands, and wherein the second quantity of the one or more rows is greater than the first quantity of the one or more rows.
13. The method of claim 1, wherein the condition of the three or more conditions and the range of the three or more ranges indicate an integrity of data stored at the one or more rows of the memory device.
14. An apparatus, comprising: at least one memory device; and at least one controller coupled with the at least one memory device and configured to cause the apparatus to: perform, at a memory device, a scrub operation comprising reading data stored in one or more rows of the memory device and detecting errors in the data of the one or more rows based at least in part on reading the data; counting a quantity of errors during the scrub operation based at least in part on reading the data stored in the one or more rows and detecting the errors in the data of the one or more rows; comparing the quantity of errors to two or more thresholds associated with three or more ranges, each range of the three or more ranges associated with a respective condition of three or more conditions associated with the memory device; and outputting, by the memory device and based at least in part on the comparing, an indicator of the quantity of errors, the outputting based at least in part on a condition of the three or more conditions and a range of the three or more ranges.
15. The apparatus of claim 14, wherein the apparatus further comprises: a register, wherein the at least one controller is coupled with the register and, to output the indicator, is further configured to cause the apparatus to: store the quantity of errors to the register of the memory device.
16. The apparatus of claim 14, wherein the memory device further comprises: a memory interface coupled with a host device, wherein the at least one controller is coupled with the memory interface and, to output the indicator, is further configured to cause the apparatus to: transmit, to the host device via the memory interface, the indicator of the quantity of errors.
17. The apparatus of claim 14, wherein the scrub operation further comprises reading error correction information stored in the one or more rows of the memory device, wherein detecting the errors in the data is based at least in part on reading the error correction information.
18. The apparatus of claim 17, wherein the apparatus further comprises: error correction circuitry, wherein the at least one controller is coupled with the error correction circuitry and is further configured to cause the apparatus to: correct, by the error correction circuitry, the errors detected in the data of the one or more rows based at least in part on reading the data and the error correction information; and write the error correction information and the data to the one or more rows of the memory device based at least in part on correcting the errors.
19. The apparatus of claim 14, wherein the apparatus further comprises: error correction circuitry, wherein the at least one controller is coupled with the error correction circuitry and is further configured to cause the apparatus to: receive, at the at least one controller, one or more write commands from a host device coupled with the memory device, wherein the one or more write commands comprise second data to be written to one or more second rows of the memory device; generating, at the error correction circuitry, error correction information based at least in part on the second data in the one or more write commands; and write the error correction information and the second data to one or more second rows of the memory device based at least in part on generating the error correction information.
20. A non-transitory computer-readable medium storing code comprising instructions which, when executed by at least one processor of an electronic device, cause the electronic device to: perform, at a memory device, a scrub operation comprising reading data stored in one or more rows of the memory device and detecting errors in the data of the one or more rows based at least in part on reading the data; counting a quantity of errors during the scrub operation based at least in part on reading the data stored in the one or more rows and detecting the errors in the data of the one or more rows; comparing the quantity of errors to two or more thresholds associated with three or more ranges, each range of the three or more ranges associated with a respective condition of three or more conditions associated with the memory device; and outputting, by the memory device and based at least in part on the comparing, an indicator of the quantity of errors, the outputting based at least in part on a condition of the three or more conditions and a range of the three or more ranges.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 8, 10-12 and 15, 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai et al. (“Errors in Flash-Memory-Based Solid-State Drives”).
Claim 1: Cai et al disclose a method, comprising:
transmitting, to a memory device, one or more commands associated with a scrub operation of the memory device (e.g. “the SSD controller periodically performs a process called garbage collection” and “refresh mechanisms have been proposed, where the stored data is periodically read, corrected, and reprogrammed.” See section 4.3); and
obtaining, by a host device and based at least in part on transmitting the one or more commands (e.g. Cai describes that the SSD controller tracks and reports errors via status registers (Section 1.3.9, pp. 10–11; Section 1.3.10, pp. 10–11). The host can obtain error indicators, such as raw bit error rates (RBER) and ECC failure rates (Section 1.3.7, p. 8)), an indicator of a quantity of errors associated with the scrub operation, the obtaining based at least in part on a range of three or more ranges associated with the quantity of errors (e.g. Cai categorizes errors into multiple ranges for adaptive management, such as “early detection,” “early failure,” and “wearout” periods (Section 3.6, pp. 27–29; Figure 21). It also teaches using error counts to bin voltage tuning (Section 4.5, pp. 35–39)).
As per claims 8 and 15, the claimed features are rejected similarly to claim 1 above.
Claim 3: Cai et al disclose the method of claim 1, further comprising: transmitting one or more write commands to the memory device, wherein the one or more write commands comprise data to be written to one or more rows of the memory device (e.g. Host writes data to SSD via write commands (Section 1.3.1, pp. 5–6); Data is written in pages (rows) (Section 1.1, p. 4). Thus, performing write operations in conjunction with scrub operations is inherent in Cai’s refresh and garbage collection processes, which involve reading and rewriting data. ).
As per claims 10 and 17, the claimed features are rejected similarly to claim 3 above.
Claim 4: Cai et al disclose the method of claim 1, further comprising: transmitting, to the memory device, a set of commands for accessing one or more rows of the memory device, wherein one or more of the set of commands indicate one or more operations for accessing the one or more rows, wherein the scrub operation is associated with the one or more operations (e.g. Refresh operations involve accessing rows (wordlines) to read and reprogram data (Section 4.3, pp. 32–34) ) and commands for accessing rows are inherent in flash operations (Section 2.3, pp. 15–16)).
As per claims 11 and 18, the claimed features are rejected similarly to claim 4 above.
Claim 5: Cai et al disclose the method of claim 4, wherein the set of commands are associated with one or more refresh operations (Section 4.3, pp. 32–34) ) and commands for accessing rows are inherent in flash operations (Section 2.3, pp. 15–16)).
As per claims 12 and 19, the claimed features are rejected similarly to claim 5 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 6, 7, 9, 11, 13, 14 and 16, 20, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cai et al as applied to claim 1 above.
Claim 2: Cai et al teach the method of claim 1, but fail to teach that obtaining the indicator comprises: polling a register of the memory device to obtain the quantity of errors. However, Cai et al teach that SSDs contain status registers used to report operation status and error information (Section 1.3.9, p. 10: “status reporting registers”) and host interfaces (AHCI/NVMe) allow the host to read device registers (Section 1.3.1, pp. 5–6). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to poll these registers from the host to obtain error counts, as polling hardware registers for device status was a well-known technique in storage systems (e.g., SMART attribute polling).
As per claims 9 and 16, the claimed features are rejected similarly to claim 2 above.
Claim 6: Cai et al teach he method of claim 1, but fail to teach transmitting, to the memory device, an indication of a rate for one or more scrub operations, wherein obtaining the indicator is based at least in part on transmitting the indication of the rate. However, Cai et al teach that adaptive refresh rates based on P/E cycle count, temperature, and retention age (Section 4.3, pp. 34–35). Therefore, a POSITA, before the effective filing date of the claimed invention, would have found it obvious to allow the host to indicate a desired scrub rate, as Cai already teaches that scrub frequency should be adaptable based on conditions. Letting the host control this parameter is a straightforward system-level design choice.
As per claims 13 and 20, the claimed features are rejected similarly to claim 6 above.
Claim 7: Cai et al teach the method of claim 1, but fail to teach that the range of the three or more ranges indicates an integrity of data stored at the memory device. However, Cai et al teach that error ranges indicate data integrity (e.g., low error rate → high integrity; high error rate → risk of data loss) (Section 3.6, pp. 27–29; Section 5.4, pp. 57–58). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, that using error ranges to infer data integrity is a direct application of Cai’s error categorization for reliability management.
As per claims 14 and 21, the claimed features are rejected similarly to claim 7 above.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 1/12/2026