Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/12/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ramachadran (Pub. No.: US 2020/0176427).
Re claim 1, Ramachadran, FIG. 8 teaches a capacitance device, comprising:
a semiconductor substrate (240+230);
a capacitor (a row of capacitor banks 102, ¶ [0032]) having at least a portion thereof disposed within the semiconductor substrate (240+230) including first and second positive terminals ([FPT]/[SPT], FIG. 2B [as shown below]) and first and second negative terminals ([FNT]/[SNT]);
a passivation layer (220), separate from the semiconductor substrate (240+230), formed over the capacitor, the first and second positive terminals ([FPT]/[SPT]) and the first and second negative terminals ([FNT]/[SNT]), the passivation layer defining a first opening (occupied by topmost surface of one of 100) over the first positive terminal, a second opening (occupied by topmost surface of another 100) over the second positive terminal, a third opening (occupied by bottommost surface of one of 100) over the first negative terminal and a fourth opening (occupied by bottommost surface of another of 100) over the second negative terminal;
a first metal bump (one 262, [0039]) disposed adjacent to the passivation layer and including first extending portions (occupied by one 100 of FIG. 7) that extend through each of the first and second openings, electrically coupling the first positive terminal to the second positive terminal; and
a second metal bump (another) disposed adjacent to the passivation layer and including second extending portions (occupied by another 100 of FIG. 7) that extend through each of the third and fourth openings, electrically coupling the first negative terminal to the second negative terminal.
Re claim 2, Ramachadran teaches the capacitance device of claim 1, wherein the first positive terminal ([FPT], FIG. 2A [as shown above]) is electrically coupled to the second positive terminal [SPT] via a first external connection (the wire formed between those two), and wherein the first negative terminal [FNT] is electrically coupled to the second negative terminal [SNT] via a second external connection (the wire formed between those two).
Re claim 3, Ramachadran, FIGS. 1/2A/8 teaches the capacitance device of claim 2, wherein the first external connection (the wire formed between those two [FPT] & [SPT]) is a first metallic connector disposed on the passivation layer (230 of FIG. 8) and extending from the first positive terminal to the second positive terminal, and wherein the second external connection is a second metallic connector disposed on the passivation layer (230) and extending from the first negative terminal to the second negative terminal (the wire formed between those two [FNT] & [SNT]).
Re claim 4, Ramachadran, FIGS. 1/2A/8 teaches the capacitance device of claim 2, wherein the first and second external connections are disposed on a separate interconnect board (left & right portion of 230 which separated by 232 of FIG. 8, [0040]) that is electrically coupled to the capacitance device.
Re claim 5, Ramachadran teaches the capacitance device of claim 1, wherein the capacitor is a first integrally formed capacitor (102 on the far left, FIG. 4), the substrate further including a second integrally formed capacitor (102 next to the far left) including a third positive terminal (upper 220 of 102 next to the far left) that is coupled to the first positive terminal of the first capacitor, the second capacitor including a third negative terminal (lower 220 of 102 next to the far left) that is coupled to the first negative terminal of the first capacitor.
Re claim 6, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal is coupled to the first positive terminal via a first electrical conductor (the wire formed between the 102 in the far left and the 102 next to it of the upper 220) disposed on the semiconductor substrate, and wherein the third negative terminal is coupled to the first negative terminal via a second electrical conductor (the wire formed between the 102 in the far left and the 102 next to it of the lower 220) disposed on the semiconductor substrate.
Re claim 7, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal is coupled to the first positive terminal via a first external connection disposed on a separate electronic device that is coupled to the capacitance device, and wherein the third negative terminal is coupled to the first negative terminal via a second external connection that is disposed on the separate electronic device.
Re claim 8, Ramachadran teaches the capacitance device of claim 1, wherein each of the first (upper 162, FIG. 1, [0032]) and the second metallic bumps (lower 162) are coupled to an external load, and wherein the capacitor is a first integrally formed capacitor (102 on the far left), the substrate further including a second integrally formed capacitor (102 next to the far left) disposed on the semiconductor substrate and including a third positive terminal (upper 220 of 102 next to the far left) and a third negative terminal (lower 220 of 102 next to the far left) that are each coupled to the external load (FIFG. 8).
Re claim 9, Ramachadran teaches the capacitance device of claim 8, wherein the first metallic bump (upper 162, FIG. 1) is electrically connected to the third positive terminal and wherein the second metallic bump (lower 162) is electrically connected to the third negative terminal.
Re claim 10, Ramachadran teaches the capacitance device of claim 8, wherein the first capacitor (one of 102 of FIG. 8) is electrically isolated from the second capacitor (102 next to it).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakaiso (Pub. No.: US 2017/0338038) in view of Ramachadran (Pub. No.: US 2020/0176427).
Re claim 1, Nakaiso teaches a capacitance device, comprising:
a semiconductor substrate (10+30, FIG. 2);
a capacitor a capacitor ([21A/20A/22A], [22A/20B/21B], & [21B/20C/22B], [0051], note that there are three capacitors exist here) having at least a portion thereof disposed within the semiconductor substrate (10+30) including first and second positive terminals (61A-E, FIG. 1-2, ¶ [0044]) and first and second negative terminals (62A-D);
a passivation layer (31-33, FIG. 2), separate from the semiconductor substrate (10+30), formed over the capacitor, the first and second positive terminals (51A/61A & 61B/51B) and the first and second negative terminals (62C/52 & 62A/52), the passivation layer defining a first opening (occupied by 61A) over the first positive terminal, a second opening (occupied by 61B) over the second positive terminal (61B/51B), a third opening (occupied by 62C) over the first negative terminal (62C/52) and a fourth opening (occupied by 62A) over the second negative terminal (62A/52);
a first connection conductor (81A/81B, FIGS. 4/5/6, note that 81A/81B are connected to positive terminals 62/52 as shown in FIG. 6) disposed adjacent to the passivation layer and including first extending portions that extend through each of the first and second openings (note that “openings that will serve as contact holes are formed in the SiO2 film by performing inductive coupling plasma reactive ion etching (ICP-RIE)”, ¶ [0062]), electrically coupling the first positive terminal to the second positive terminal; and
a second connection conductor (71A/71B, FIGS. 4/5/6, note that 71A/71B are connected to negative terminals 61/51 as shown in FIG. 6) disposed adjacent to the passivation layer and including second extending portions that extend through each of the third and fourth openings (note that “openings that will serve as contact holes are formed in the SiO2 film by performing inductive coupling plasma reactive ion etching (ICP-RIE)”, ¶ [0062]), electrically coupling the first negative terminal to the second negative terminal.
Nakaiso fails to teach a metallic bump.
Ramachadran teaches a metallic bump (162, FIG. 1, ¶ [0032]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of providing the means for forming the connection as taught by Ramachadran, [0032].
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Re claim 2, in the combination, Ramachadran teaches the capacitance device of claim 1, wherein the first positive terminal ([FPT], FIG. 2A [as shown above]) is electrically coupled to the second positive terminal [SPT] via a first external connection (the wire formed between those two), and wherein the first negative terminal [FNT] is electrically coupled to the second negative terminal [SNT] via a second external connection (the wire formed between those two).
Re claim 3, in the combination, Ramachadran, FIGS. 1/2A/8 teaches the capacitance device of claim 2, wherein the first external connection (the wire formed between those two [FPT] & [SPT]) is a first metallic connector disposed on the passivation layer (230 of FIG. 8) and extending from the first positive terminal to the second positive terminal, and wherein the second external connection is a second metallic connector disposed on the passivation layer (230) and extending from the first negative terminal to the second negative terminal (the wire formed between those two [FNT] & [SNT]).
Re claim 4, in the combination, Ramachadran, FIGS. 1/2A/8 teaches the capacitance device of claim 2, wherein the first and second external connections are disposed on a separate interconnect board (left & right portion of 230 which separated by 232 of FIG. 8, [0040]) that is electrically coupled to the capacitance device.
Re claim 5, in the combination, Ramachadran teaches the capacitance device of claim 1, wherein the capacitor is a first integrally formed capacitor (102 on the far left, FIG. 4), the substrate further including a second integrally formed capacitor (102 next to the far left) including a third positive terminal (upper 220 of 102 next to the far left) that is coupled to the first positive terminal of the first capacitor, the second capacitor including a third negative terminal (lower 220 of 102 next to the far left) that is coupled to the first negative terminal of the first capacitor.
Re claim 6, in the combination, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal is coupled to the first positive terminal via a first electrical conductor (the wire formed between the 102 in the far left and the 102 next to it of the upper 220) disposed on the semiconductor substrate, and wherein the third negative terminal is coupled to the first negative terminal via a second electrical conductor (the wire formed between the 102 in the far left and the 102 next to it of the lower 220) disposed on the semiconductor substrate.
Re claim 7, in the combination, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal is coupled to the first positive terminal via a first external connection disposed on a separate electronic device that is coupled to the capacitance device, and wherein the third negative terminal is coupled to the first negative terminal via a second external connection that is disposed on the separate electronic device.
Re claim 8, in the combination, Ramachadran teaches the capacitance device of claim 1, wherein each of the first (upper 162, FIG. 1, [0032]) and the second metallic bumps (lower 162) are coupled to an external load, and wherein the capacitor is a first integrally formed capacitor (102 on the far left), the substrate further including a second integrally formed capacitor (102 next to the far left) disposed on the semiconductor substrate and including a third positive terminal (upper 220 of 102 next to the far left) and a third negative terminal (lower 220 of 102 next to the far left) that are each coupled to the external load (FIFG. 8).
Re claim 9, in the combination, Ramachadran teaches the capacitance device of claim 8, wherein the first metallic bump (upper 162, FIG. 1) is electrically connected to the third positive terminal and wherein the second metallic bump (lower 162) is electrically connected to the third negative terminal.
Re claim 10, in the combination, Ramachadran teaches the capacitance device of claim 8, wherein the first capacitor (one of 102 of FIG. 8) is electrically isolated from the second capacitor (102 next to it).
Response to Arguments
Applicant's arguments filed 01/12/2026 have been fully considered but they are not persuasive because Ramachadran, FIG. 8 teaches a capacitance device, comprising:
a semiconductor substrate (240+230);
a capacitor (a row of capacitor banks 102, ¶ [0032]) having at least a portion thereof disposed within the semiconductor substrate (240+230) including first and second positive terminals ([FPT]/[SPT], FIG. 2B [as shown below]) and first and second negative terminals ([FNT]/[SNT]);
a passivation layer (220), separate from the semiconductor substrate (240+230), formed over the capacitor; and
Nakaiso teaches a capacitance device, comprising:
a semiconductor substrate (10+30, FIG. 2);
a capacitor a capacitor ([21A/20A/22A], [22A/20B/21B], & [21B/20C/22B], [0051], note that there are three capacitors exist here) having at least a portion thereof disposed within the semiconductor substrate (10+30) including first and second positive terminals (61A-E, FIG. 1-2, ¶ [0044]) and first and second negative terminals (62A-D);
a passivation layer (31-33, FIG. 2), separate from the semiconductor substrate (10+30), formed over the capacitor.
For the above reasons, it is believed that the rejections should be sustained.
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893