Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 5-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ramachadran (Pub. No.: US 2020/0176427).
Re claim 1, Ramachadran, FIG. 8 teaches a capacitance device, comprising:
a semiconductor substrate (240+230);
a capacitor (a row of capacitor banks 102, ¶ [0032]) including first and second positive terminals ([FPT]/[SPT], FIGS. 2A/2B [as shown below]) and first and second negative terminals ([FNT]/[SNT]);
a passivation layer (220/151, FIGS. 8/13), separate from the semiconductor substrate (240+230), formed over the capacitor, the first and second positive terminals ([FPT]/[SPT]) and the first and second negative terminals ([FNT]/[SNT]), the passivation layer defining a first opening (occupied by topmost surface of one of 100) over the first positive terminal, a second opening (occupied by topmost surface of another 100) over the second positive terminal, a third opening (occupied by bottommost surface of one of 100) over the first negative terminal and a fourth opening (occupied by bottommost surface of another of 100) over the second negative terminal;
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a first metal bump (one 262/162, FIGS. 1/8/13, [0039]) having a first perimeter ([FP], FIG. 1 [as shown above]) and disposed adjacent to the passivation layer (220/151) including first extending portions (occupied by one 100 of FIG. 7) defined within the first perimeter [FP] and that extend through each of the first and second openings, electrically coupling the first positive terminal to the second positive terminal; and
a second metal bump (another one 262/162) having a second perimeter [SP] and disposed adjacent to the passivation layer (220/151, FIGS. 8/13) and including second extending portions (occupied by another 100 of FIG. 7) defined within the second perimeter [SP] and that extend through each of the third and fourth openings, electrically coupling the first negative terminal to the second negative terminal.
Re claim 5, Ramachadran teaches the capacitance device of claim 1, wherein the capacitor is a first capacitor (102 on the far left, FIG. 4), the capacitance device further including a second capacitor (102 next to the far left) including a third positive terminal (upper 220 of 102 next to the far left) that is coupled to the first positive terminal of the first capacitor, the second capacitor including a third negative terminal (lower 220 of 102 next to the far left) that is coupled to the first negative terminal of the first capacitor.
Re claim 6, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal is coupled to the first positive terminal via the first metallic bump (one 262/162), and wherein the third negative terminal is coupled to the first negative terminal via the second metallic bump (another one 262/162).
Re claim 7, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal (FIGS. 3-4) is defined within the first perimeter (within the upeer dash-dash boundary of FIG. 3) and, and wherein the third negative terminal is defined within the second perimeter (within the lower dash-dash boundary of FIG. 3).
Re claim 8, Ramachadran teaches the capacitance device of claim 1, wherein each of the first (upper 162, FIG. 1, [0032]) and the second metallic bumps (lower 162) are coupled to an external load, and wherein the capacitor is a first integrally formed capacitor (102 on the far left), the semiconductor substrate further including a second integrally formed capacitor (102 next to the far left) disposed on the semiconductor substrate and including a third positive terminal (upper 220 of 102 next to the far left) and a third negative terminal (lower 220 of 102 next to the far left) that are each coupled to the external load (FIG. 8).
Re claim 9, Ramachadran teaches the capacitance device of claim 8, wherein the first metallic bump (upper 162, FIG. 1) is electrically connected to the third positive terminal and wherein the second metallic bump (lower 162) is electrically connected to the third negative terminal.
Re claim 10, Ramachadran teaches the capacitance device of claim 8, wherein the first capacitor (one of 102 of FIG. 8) is electrically isolated from the second capacitor (102 next to it).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakaiso (Pub. No.: US 2017/0338038) in view of Ramachadran (Pub. No.: US 2020/0176427).
Re claim 1, Nakaiso teaches a capacitance device, comprising:
a semiconductor substrate (10+30, FIG. 2);
a capacitor a capacitor ([21A/20A/22A], [22A/20B/21B], & [21B/20C/22B], [0051], note that there are three capacitors exist here) having at least a portion thereof disposed within the semiconductor substrate (10+30) including first and second positive terminals (61A-E, FIG. 1-2, ¶ [0044]) and first and second negative terminals (62A-D);
a passivation layer (31-33, FIG. 2), separate from the semiconductor substrate (10+30), formed over the capacitor, the first and second positive terminals (51A/61A & 61B/51B) and the first and second negative terminals (62C/52 & 62A/52), the passivation layer defining a first opening (occupied by 61A) over the first positive terminal, a second opening (occupied by 61B) over the second positive terminal (61B/51B), a third opening (occupied by 62C) over the first negative terminal (62C/52) and a fourth opening (occupied by 62A) over the second negative terminal (62A/52);
a first connection conductor (81A/81B, FIGS. 4/5/6, note that 81A/81B are connected to positive terminals 62/52 as shown in FIG. 6) disposed adjacent to the passivation layer and including first extending portions that extend through each of the first and second openings (note that “openings that will serve as contact holes are formed in the SiO2 film by performing inductive coupling plasma reactive ion etching (ICP-RIE)”, ¶ [0062]), electrically coupling the first positive terminal to the second positive terminal; and
a second connection conductor (71A/71B, FIGS. 4/5/6, note that 71A/71B are connected to negative terminals 61/51 as shown in FIG. 6) disposed adjacent to the passivation layer and including second extending portions that extend through each of the third and fourth openings (note that “openings that will serve as contact holes are formed in the SiO2 film by performing inductive coupling plasma reactive ion etching (ICP-RIE)”, ¶ [0062]), electrically coupling the first negative terminal to the second negative terminal.
Nakaiso fails to teach a metallic bump; and a first metal bump having a first perimeter and disposed adjacent to the passivation layer including first extending portions defined within the first perimeter; and
a second metal bump having a second perimeter and disposed adjacent to the passivation layer and including second extending portions defined within the second perimeter.
Ramachadran teaches a metallic bump (162, FIG. 1, ¶ [0032]); and a first metal bump (one 262/162, FIGS. 1/8/13, [0039]) having a first perimeter ([FP], FIG. 1 [as shown above]) and disposed adjacent to the passivation layer (220/151) including first extending portions (occupied by one 100 of FIG. 7) defined within the first perimeter [FP]; and
a second metal bump (another one 262/162) having a second perimeter [SP] and disposed adjacent to the passivation layer (220/151, FIGS. 8/13) and including second extending portions (occupied by another 100 of FIG. 7) defined within the second perimeter [SP]
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of providing the means for forming the connection as taught by Ramachadran, [0032].
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Re claim 5, Ramachadran teaches the capacitance device of claim 1, wherein the capacitor is a first capacitor (102 on the far left, FIG. 4), the capacitance device further including a second capacitor (102 next to the far left) including a third positive terminal (upper 220 of 102 next to the far left) that is coupled to the first positive terminal of the first capacitor, the second capacitor including a third negative terminal (lower 220 of 102 next to the far left) that is coupled to the first negative terminal of the first capacitor.
Re claim 6, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal is coupled to the first positive terminal via the first metallic bump (one 262/162, FIGS. 3/4), and wherein the third negative terminal is coupled to the first negative terminal via the second metallic bump (another one 262/162).
Re claim 7, Ramachadran teaches the capacitance device of claim 5, wherein the third positive terminal (FIGS. 3-4) is defined within the first perimeter (within the upper dash-dash boundary of FIG. 3) and, and wherein the third negative terminal is defined within the second perimeter (within the lower dash-dash boundary of FIG. 3).
Re claim 8, Ramachadran teaches the capacitance device of claim 1, wherein each of the first (upper 162, FIG. 1, [0032]) and the second metallic bumps (lower 162) are coupled to an external load, and wherein the capacitor is a first integrally formed capacitor (102 on the far left), the semiconductor substrate further including a second integrally formed capacitor (102 next to the far left) disposed on the semiconductor substrate and including a third positive terminal (upper 220 of 102 next to the far left) and a third negative terminal (lower 220 of 102 next to the far left) that are each coupled to the external load (FIG. 8).
Re claim 9, in the combination, Ramachadran teaches the capacitance device of claim 8, wherein the first metallic bump (upper 162, FIG. 1) is electrically connected to the third positive terminal and wherein the second metallic bump (lower 162) is electrically connected to the third negative terminal.
Re claim 10, in the combination, Ramachadran teaches the capacitance device of claim 8, wherein the first capacitor (one of 102 of FIG. 8) is electrically isolated from the second capacitor (102 next to it).
Response to Arguments
Applicant's arguments filed 07/14/2026 have been fully considered but they are not persuasive because Ramachadran, FIGS. 1, 8 and 13 still reads on:
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a first metal bump (one 262/162, FIGS. 1/8/13, [0039]) having a first perimeter ([FP], FIG. 1 [as shown above]) and disposed adjacent to the passivation layer (220/151) including first extending portions (occupied by one 100 of FIG. 7) defined within the first perimeter [FP] and that extend through each of the first and second openings, electrically coupling the first positive terminal to the second positive terminal; and
a second metal bump (another one 262/162) having a second perimeter [SP] and disposed adjacent to the passivation layer (220/151, FIGS. 8/13) and including second extending portions (occupied by another 100 of FIG. 7) defined within the second perimeter [SP] and that extend through each of the third and fourth openings, electrically coupling the first negative terminal to the second negative terminal.
For the above reasons, it is believed that the rejections should be sustained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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