Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the remarks filed July 23, 2026.
This application has been examined. Claims 1-20 are pending in the application, and Claims 1-2, 13-14 stand rejected.
Specification
The objection to the title of the invention set forth in the prior Office Action is acknowledged as addressed by Applicant's amendment of the title in the Amendment filed July 23, 2026. Subject to confirmation that the substitute title is descriptive of the claimed invention (see header table above), the objection to the specification is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 13-14 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Alston (US 6,055,285) in view of Nair et al. (US 2020/0409408) ("Nair").
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Alston and Boles references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 1, Alston discloses a circuit comprising: an elastic buffer configured to operate according to a read clock associated with a read domain and a write clock associated with a write domain, wherein the elastic buffer is configured to: generate a first signal associated with the write domain and indicative of a first difference between a read pointer and a write pointer (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Alston discloses write controller 140 monitors the value of the write address counter 170 - operating in the CLOCK1/write domain - against the synchronized read address pointer on synchronized read pointer bus 216, which second synchronization circuit 212 generates by latching the read pointer through an input-latch/output-latch pair under timed enable signals so that the value is stable with respect to CLOCK1, in order to determine when the next addressed storage location has not been read since the last write operation). See col. 3:39-5:5; 7:32-63; col. 8:10-51; col. 9:4-48);
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and generate a second signal associated with the read domain and indicative of a second difference between the read pointer and the write pointer (in Alston, read controller 142 monitors the value of the read address counter 172 - operating in the CLOCK2/read domain - against the synchronized write address pointer on synchronized write pointer bus 214, generated by first synchronization circuit 210 using the same latched, timed-enable architecture stabilized with respect to CLOCK2, in order to determine when all data currently stored has been transferred; Alston, col. 6:51-7:25; col. 8:10-51). But Alston does not specifically disclose a logic circuit configured to determine a phase difference between the read clock and the write clock based on the first signal and the second signal. Alston's synchronized-pointer comparisons are used only to gate the write and read handshake signals (col. 6:34-57) and are not shown as inputs to any circuit that derives a cross-domain clock phase relationship. In the same field of endeavor of clock-domain-crossing FIFO circuits, Nair et al. disclose a logic circuit configured to determine a phase difference between the read clock and the write clock (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Nair discloses a FIFO training logic circuit 130 that receives, from a pulse generation circuit of read pointer logic 125, timing pulses generated at a predetermined point of the read pointer's (124) cycle (Nair, [0015], [0031]), and that employs a sample counter (404) to count the number of such timing pulses occurring during the advance period of the write pointer (122) between increments (Nair, [0039]-[0040]). FIFO training logic circuit 130 measures the relationship between the timing pulses (tied to the read-domain pointer) and the write pointer's advance period (tied to the write-domain pointer) and, based on that measured relationship, sends a control signal to a clock phase adjustment circuit to adjust the phase of the write clock (Txclk 20) (Nair, [0013], [0017]); when the measured relationship reaches a desired state (a “zero error point”), FIFO training logic 130 issues a Write Pointer Sync signal that resets the write pointer to be synchronous with the read pointer (Nair, [0017]-[0018]). Nair thus discloses a logic circuit that determines, from information indicative of the read-domain and write-domain pointer activity, a phase relationship between the read clock and the write clock, and that uses the determined relationship to adjust clock phase).
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It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Alston's write/read pointer synchronization circuitry to further include a phase-comparison and clock-phase-adjustment logic circuit that operates on the domain-local pointer-difference information, as taught by Nair, because Alston already generates and stabilizes the requisite cross-domain pointer information for exactly this purpose (col. 7:13-32), Nair establishes that such pointer-derived, cross-domain timing information is suitable input for deriving a clock phase relationship and driving an active phase adjustment, and combining Alston's known FIFO pointer-synchronization elements with Nair's known pointer-based phase-determination technique according to their established methods would have yielded the predictable result of a phase-aware elastic buffer, with a reasonable expectation of success because both references operate on structurally analogous dual read-pointer/write-pointer FIFO clock-domain-crossing architectures. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007); MPEP § 2143(A).
In regard to claim 13, Alston discloses a method comprising: generating, by an elastic buffer of a physical coding sublayer (PCS) circuit, a first signal associated with a write domain and indicative of a first difference between a read pointer and a write pointer, wherein the elastic buffer operates according to a read clock associated with a read domain and a write clock associated with the write domain (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Alston discloses a method comprising generating, by an elastic buffer (FIFO buffer memory 110) of a physical coding sublayer (PCS) circuit, a first signal associated with a write domain and indicative of a first difference between a read pointer and a write pointer, wherein the elastic buffer operates according to a read clock (CLOCK2) associated with a read domain and a write clock (CLOCK1) associated with the write domain (write controller 140 compares write address counter 170 against the synchronized read pointer on bus 216, stabilized with respect to CLOCK1 by the latched, timed-enable synchronization architecture; Alston, col. 3:39-5:5; 7:32-63; col. 8:10-51; col. 9:4-48);
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generating, by the elastic buffer, a second signal associated with the read domain and indicative of a second difference between the read pointer and the write pointer (in Alston, generating, by the elastic buffer, a second signal associated with the read domain and indicative of a second difference between the read pointer and the write pointer (read controller 142 compares read address counter 172 against the synchronized write pointer on bus 214, stabilized with respect to CLOCK2 by the same architecture; Alston, col. 6:51-7:25; col. 8:10-51). But Alston does not specifically disclose determining, by a logic circuit, a phase difference between the read clock and the write clock based on the first signal and the second signal, for the reasons discussed above with respect to claim 1. In the same field of endeavor, Nair discloses a logic circuit configured to determine a phase difference between the read clock and the write clock. In the same field of endeavor, Nair discloses a logic circuit configured to determine a phase difference between the read clock and the write clock (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Nair teaches, determining, by a FIFO training logic circuit 130, a relationship between timing pulses tied to the read pointer's (124) cyclical position (Nair, [0015], [0020], [0031]) and the advance period of the write pointer (122), as measured by a sample counter 404 (Nair, [0022]-[0024), and adjusting the phase of the write clock (Txclk 20) based on that relationship via a clock phase adjustment circuit (Nair, [0029]-[0030]), including resetting the write pointer to be synchronous with the read pointer once a desired (“zero error”) relationship is reached (Nair, [0020]; [0025]-[0027]).
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It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Alston's method to further include determining a phase difference between the read clock and write clock from the domain-local pointer-difference information, as taught by Nair, for the same reasons and with the same reasonable expectation of success discussed above with respect to claim 1.
6. Claims 2, 14 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Alston in view of Nair, and further in view of Boles et al. (US 7,123,675) ("Boles").
In regard to claims 2, 14, Alston in view of Nair discloses the PCS circuit of claim 1, but does not expressly disclose that the read clock and the write clock have the same clock rate. In the same field of endeavor of clock recovery and synchronization for high-speed serial links, Boles teaches wherein the read clock and the write clock have the same clock rate (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Boles teaches, a clock and data recovery circuit 202 that recovers a transmitter clock with a bounded phase relationship with respect to an incoming data signal, such that the recovered transmitter clock and the incoming data signal have the same frequency, with their relative phase remaining within a given range (Boles, col. 4:3-65)).
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It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to further configure the read clock and write clock of the Alston/Nair PCS circuit to have the same clock rate, as taught by Boles, because Boles demonstrates that clocks bridging a receive/transmit or read/write boundary in high-speed serial links are commonly matched in frequency and differ only in phase, and applying this known clock-rate relationship to Alston's FIFO domains would predictably configure the buffer as a same-rate, phase-only clock-domain-crossing circuit - precisely the type of circuit Nair's training logic 130 is designed to phase-align - with a reasonable expectation of success.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
7. Claims 3-12, 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The Examiner's statement of reasons, for claims 3, 6, 13, 17, can be found in the previous Office Action.
Response to Arguments
This rejection revises the § 103 rejection of claims 1-2 and 13-14 set forth in the non-final Office action mailed 04/23/2026. Boles (US 7,123,675) is no longer relied upon for the “logic circuit configured to determine a phase difference between the read clock and the write clock” limitation of claims 1 and 13. On re-verification against the reference text, the previously cited passage (Boles, col. 6:l. 56-7:30) describes subtractor circuit 404 computing the distance between the write and read pointers, which Boles itself characterizes as “the latency of a data word in the FIFO 204 prior to being read” and “a direct measurement of the delay experienced as a result of using the FIFO” - i.e., a FIFO fill-level/latency measurement, not a clock-to-clock phase difference. Boles' only genuine phase teaching (the CDR bounded-phase relationship at col. 5:20-27, and the word-alignment/skew value carried alongside data as signal 210) is not derived from, and does not read on, the claimed first and second pointer-difference signals. Boles (col. 5:20-27) is retained solely for the same-clock-rate limitation of claims 2 and 14, which that passage independently supports. Nair (US 2020/0409408) is newly applied for the phase-difference logic-circuit limitation of claims 1 and 13, per the mapping above; this citation has been verified against the reference text (paragraphs [0013], [0015], [0017]-[0018], [0031], [0039]-[0040]).
Because this correction introduces a new secondary reference and is not necessitated by an applicant amendment, this action should be treated as a second non-final Office action. See MPEP § 706.07(a)-(b).
No change is made to the allowable-subject-matter finding for claims 3, 6, 13’s dependent claims, 15-20 (dual-domain subtraction generating the first/second signals, and the gearbox coupled to the elastic buffer), carried forward unchanged from the 04/23/2026 action.
Conclusion
9. Claims 1-2, 13-14 are rejected. Claims 3-12 and 15-20 are objected.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
Prosecution Insights