DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to communication(s) received on 02/19/2026. There are a total 20 clams pending in the application; claims 1, 11, and 16 have been amended; no claims has been added or canceled.
IFORMATION CONCENING DRAWING:
3. Application’s drawing submitted on 10/23/2024 are acceptable for examination purposes.
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bemists “Bemist” (US 10387078 B1) in view of Malwankar et al. “Malwankar (US 10,175,891 B1).
4. Regarding claim 1, Bemist teaches or suggests:
“A system (e.g., Fig. 5), comprising: a processor;” (e.g., Fig. 5, host processor 502)
“and a device;” (e.g., Fig. 5, col. 10, line 63 to col. 11, line 2, The NV Me storage device 506).
“a memory accessible to the processor (e.g., Fig. 5, col. 11, lines 22-23, the host processor 502 creates and writes commands in submission queues SQ1 512.sub.1, SQ2 512.sub.2, and SQ3 512.sub.3.) and to the device,” (e.g., Fig. 5, col. 11, lines 29-35, The NV Me controller 508 fetches commands from the submission queues 512.sub.1, 512.sub.2, and 512.sub.3 queues and executes the commands Upon completion of the commands, the NV Me controller 508 writes completion entries that are ultimately directed to completion queues CQ1 514.sub.1, CQ2 514.sub.2, and CQ3 514.sub.3. In some examples, each of the completion queues 514.sub.1, 514.sub.2, and 514.sub.3).
“the memory including a queue and a buffer, the queue including an entry (e.g., col. 1, lines 45-48, The submission and completion queues may be, for example, circular buffers. The circular buffers each include head and tail pointers that mark the ends of the current entries of the queue).
“wherein the processor is configured to place a request in the entry of the queue and the device is configured to process the request using the buffer,” (e.g., Fig. 5, col. 11, lines 22-23, the host processor 502 creates and writes commands in submission queues SQ1 512.sub.1, SQ2 512.sub.2, and SQ3 512.sub.3; Fig. 2, col. 7, lines 11-14, the host thereby determines that the queue 210 is empty and can be filled up to the maximum size of the queue (which in this particular example is sixteen entries); Fig. 2, col. 10, lines 15-16, Each host submission queue is a contiguous or non-contiguous ring buffer). However, Bemist does not appear to expressly teach while Malwankar discloses:
“the buffer identified by the entry;” (e.g., Fig. 3, col. 16, lines 50 to col. 17, line 64) for identifying a number of data blocks (e.g., buffer) associated with an entry of write request in the write request queue. Malwankar a system comprising a plurality of host computing devices (e.g., 104A to 104x) accessing a storage sever 101. The storage server comprises a plurality of I/O controllers (e.g., 108A to 108Y) and a management module. The I/O controllers configured to connect and access a plurality SSD (e.g., storage devices) via a switch (see Fig. 1). Fig. 2 of Malwankar shows a configuration of an I/O controller comprising a plurality queues including a Write request queue 223 and buffer 222. Malwankar further teaches that the I/O controller may include main memory comprising volatile memory such as DRAM. The volatile memory is used for buffer (e.g., see col. 3, lines 33-58 of Malwankar). Fig. 3 of Malwankar teaches a write request queue 310 comprising a plurality of entries (e.g., write entries 315A to 315N) and a buffer 320 comprising a plurality entries (e.g., a plurality or pool of memory blocks). Fig 3 and corresponding text description show/teach that each entry in the write request queue associated (e.g., identifies) a number or a set of memory blocks (e.g., buffer entries associated with a queue entry).
“wherein the processor and the device also communicate using a system of submission queue/completion queue pairs.” (e.g., Fig. 2, col. 12, lines 15-24) placing a submission queue 280 and a completion queue 285 in the SSD I/O controller.
Disclosures by Bemist and Malwankar are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the Adaptive Control of Host Queue depth taught by Bemist to include the write request queue taught by Malwankar.
The motivation for including the write request queue is overall performance (e.g.,, see col. 5, line 58 to col. 6, line 6 of Malwankar).
Therefore, it would have been obvious to combine teaching of Malwankar with Bemist to obtain the invention as specified in the claim.
5. Regarding claim 11 Bemist teaches or suggests:
“A method (e.g., Fig. 8), comprising: placing, by a processor, a request in an entry of a queue in a memory, the memory further including a buffer;” (e.g., col. 1, lines 20-24, a host device writes data storage device commands, such as read commands, write commands, and administrative commands, into submission queues that are implemented in host memory; Fig. 5, col. 11, lines 22-23, the host processor 502 creates and writes commands in submission queues SQ1 512.sub.1, SQ2 512.sub.2, and SQ3 512.sub.3.)
“associating, by the processor, the request in the entry of the queue with a buffer in the memory;” (e.g., col. 10, lines 15-16, Each host submission queue is a contiguous or non-contiguous ring buffer; Fig. 2, In the first scenario 202, with throttling disabled (i.e. No Submission Throttling), the external head and tail pointers are the same as the internal head and tail pointers (which, as noted, are both equal, thus indicating the queue is empty). By reading head and tail pointers that are the same, the host thereby determines that the queue 210 is empty and can be filled up to the maximum size of the queue (which in this particular example is sixteen entries). Hence, in the first scenario 202, the external head pointer reported to the host is not adjusted or changed relative to the actual internal head pointer and so no host throttling is performed. The effective queue depth is therefore the same as the actual queue depth (which, in this example, is sixteen). The host thus proceeds as normal, adding commands as needed to the submission queue 210). Fig. 2 shows a circular buffer comprising sixteen entries or slot associated with a submission queue and shows position of a head pointer relative to tail pointer as entries filled (e.g., ring or circular buffer throttling).
“notifying a device, by the processor, that the request has been placed in the entry of the queue;” (e.g., col. 10, lines 30-33, the host notifies the NVM data storage controller that commands are available in the queue by, e.g., issuing a memory write to a relevant doorbell register). However, Bemist does not appear to expressly teach while Malwankar discloses:
“retrieving, by the processor, a result of the request based at least in part on the entry of the queue and the buffer,” (e.g., Fig. 5, col. 19, lines 14-26, At block 515, processing logic retrieves the data block associated with the logical address from the buffer. At block 520, processing logic returns a response to the read request received at block 505 with the data block retrieved from the buffer).
“wherein the processor and the device also communicate using a system of submission queue/completion queue pairs.” (e.g., Fig. 2, col. 12, lines 15-24) placing a submission queue 280 and completion queue 285 in the SSD I/O controller. The motivation for combining is based on the same rational recited above with respect to claim 1.
6. Regarding claim 16 Bemist teaches or suggests:
“A method (e.g., Fig. 8), comprising: receiving, from a processor at a device, a notification that a request has been placed in an entry of a queue in a memory the memory further including a buffer;” (e.g., col. 10, lines 30-33, the host notifies the NVM data storage controller that commands are available in the queue by, e.g., issuing a memory write to a relevant doorbell register).
“accessing, by the device, the request from the entry of the queue in the memory;” (e.g., Fig. 5, col. 11, lines 29-34, The NV Me controller 508 fetches commands from the submission queues 512.sub.1, 512.sub.2, and 512.sub.3 and executes the commands Upon completion of the commands, the NV Me controller 508 writes completion entries that are ultimately directed to completion queues CQ1 514.sub.1, CQ2 514.sub.2, and CQ3 514.sub.3).
“and processing, by the device, the request using at least one of the device and a buffer in the memory.” (e.g., Fig. 5 col. 11, lines 10-42; Fig. 6, col. 11, lines 43-67). Fig. 5 shows a host device comprising a memory and a processor. The processor generates a plurality of queues accessible to the host processor and the device controller. The processor places the commands into a plurality submission queues. The device controller fetches the executes the commands and stores the completed results in completion queues. Fig. 6 shows an exemplary structure of a completion entry 600 for a particular command issued to the NV Me storage device. Fig. 6 shows an entry in completion queue (CQ) associated with a specific command. The entry 600 comprises a plurality fields. For example. Field 606 SQ identifier from which the command retrieved and SQ head pointer (e.g., indicating start of ring or circular buffer) associated with the queue. Fig. 7 describe more detail components of NV Me controller for executing a read command. Fig. 8 is a flowchart describing a method of executing a specific read command fetched from a SQ and storing the result in CQ associated with SQ in the host memory for host processor to access.
“wherein the processor and the device also communicate using a system of submission queue/completion queue pairs.” However, Bemist does not appear to expressly teach while Malwankar discloses:
“wherein the processor and the device also communicate using a system of submission queue/completion queue pairs.” (e.g., Fig. 2, col. 12, lines 15-24) placing a submission queue 280 and completion queue 285 in the SSD I/O controller. The motivation for combining is based on the same rational recited above with respect to claim 1.
7. Regarding claim 2 Bemist further teaches:
“wherein the device includes a storage device.” (e.g., Fig. 5, NV Me storage device 506)
8. Regarding claim 3 Bemist further teaches:
“wherein the device supports a Non-Volatile Memory Express (NV Me) protocol.” (e.g., Fig. 5, col. 11, lines 10-16, The NV Me controller 508 controls access to the non-volatile memory 510 such as a NAND. The NV Me controller 508 thus may be a non-volatile memory controller that implements or supports the NV Me protocol).
9. Regarding claim 4 Bemist further teaches:
“wherein the queue includes a ring buffer, the ring buffer including a head pointer and a tail pointer.” (e.g., col. 1, lines 45-48, The submission and completion queues may be, for example, circular buffers. The circular buffers each include head and tail pointers).
10. Regarding claims 5-7 designating buffer size and a device unit size is a design choice. Furthermore, Malwankar teaches that The buffer manager can utilize threshold buffer sizes to manage the amount of data stored in the buffer so that it remains efficiently tuned to retain only as much data as would be needed to balance minimized read latency times against wasted resources on the storage server.
(e.g., see col. 2, lines 25-45 of Malwankar)
11. Regarding claim 8 Bemist further teaches:
“wherein the request includes a control, a status, (e.g., Fig. 11, col. 15, lines 13-18, the NVM data storage controller fetches commands from the host and evaluates whether those commands … namespace identifiers (IDs) and/or other parameters)).
Malwankar discloses: “a buffer identifier (ID) for the buffer” (e.g., Fig. 3, col. 16, lines 50 to col. 17, line 64) each write entry in a write request quest queue comprises a pointer to an associated buffer (e.g., memory blocks). The pointer identifies the associated buffer.
12. Regarding claim 9 Malwankar further teaches:
Designating number numbers to the entries and the buffer is a design choice. However, teaches the limitation
“wherein: the queue includes a first number of entries;” (e.g., Fig. 3 and corresponding text description of Malwankar: write request queue 310 comprises entries of 315A to 315N (4 entries shown)
“the memory includes a second number of buffers;” (Fig. 3: each entry is associate with a buffer comprising a plurality of blocks with a pointer or arrow identifies the corresponding buffer).
“and the first number of entries is equal to the second number of buffers.” (Fig. 3: each entry in write request queue 310 is associated with a buffer, there are same number buffers as numbers of entries).
12. Regarding claim 10 Bemist further teaches:
“wherein the device includes a notification mechanism for the processor to notify the device that the request has been placed in the entry of the queue.” (e.g., col. 10, lines 30-33, During NVM usage, the host notifies the NVM data storage controller that commands are available in the queue by, e.g., issuing a memory write to a relevant doorbell register).
13. Regarding claim 12 Bemist further teaches:
“wherein: the device includes a storage device;” (e.g., Fig. 5, NV Me storage device)
“the request includes a read request;” (e.g., col. 1, line 21-24, a host device writes data storage device commands, such as read commands, write commands, and administrative commands, into submission queues that are implemented in host memory). However, Bemist does not appear to expressly teach while Malwankar discloses:
“retrieving, by the processor, the result of the request based at least in part on the entry of the queue and the buffer includes reading data from the buffer based at least in part on the storage device processing the request in the entry of the queue.” (e.g., Fig. 5, col. 19, lines 14-26, At block 515, processing logic retrieves the data block associated with the logical address from the buffer).
14. Regarding claim 13 Bemist further teaches:
“allocating, by the processor, the queue in the memory; and allocating, by the processor, the buffer in the memory.” (e.g., Fig. 5, col. 11, lines 39-42, the host device 500 may create the set of submission queues (e.g., the queues 512.sub.1, 512.sub.2, and 512.sub.3) and the corresponding set of completion queues (e.g., the queues 514.sub.1, 514.sub.2, and 514.sub.3)). Host comprises a processor.
15. Regarding claim 14 Bemist further teaches:
“notifying the device, by the processor, about the queue and the buffer.” (e.g., col. 10, lines 30-35, e.g., col. 10, lines 30-33, During NVM usage, the host notifies the NVM data storage controller that commands are available in the queue by, e.g., issuing a memory write to a relevant doorbell register in storage device).
16. Regarding claim 15 Bemist further teaches:
“notifying the device, by the processor, of an interval.” (e.g., Fig. 14, col. 18, lines 31-53). Host timeout interval associated with throttling circular buffer (see also Fig. 2 of Bemist).
17. Regarding claim 17 Bemist further teaches:
“updating a status in the entry of the queue.” (e.g., Fig. 6, col. 11, lines 59-61, a Status field 610 of completion entry 600 are cleared to a zero value (unless an error occurs). The CQ status is being set or updated with occurrence of an error.
18. Regarding claim 18 Bemist further teaches:
“wherein processing, by the device, the request using at least one of the device and the buffer in the memory includes identifying the buffer based at least (e.g., col. 1, lines 45-48, The submission and completion queues may be, for example, circular buffers. The circular buffers each include head and tail pointers; Fig. 5, col. 11, lines 10-42). The controller of the storage device 506 fetches the command from SQ located in memory of the and executes the command and post or stores the results in CQ located in the host memory. Bemist does not expressly teach while
Malwankar discloses: “identifying the buffer based at least in part on a buffer ID in the request in the entry of the queue” (e.g., Fig. 3, col. 16, lines 50 to col. 17, line 64) for identifying a number of data blocks (e.g., buffer) associated with an entry of write request in the write request queue.
19. Regarding claim 19 Bemist further teaches:
“wherein: the device includes a storage device;” (e.g., Fig. 5, NV Me storage device 506).
“the request includes a read request;” (e.g., col. 1, lines 21-22, a host device writes data storage device commands, such as read commands).
“and processing, by the device, the request using at least one of the device (e.g., Fig. 5, storage device 506) and the buffer in the memory device (e.g., Fig. 5, SQ 512.sub.1) includes: reading a data from the storage device based at least in part on the request;” (e.g., col. 1, lines 20-24, a host device writes data storage device commands, such as read commands, write commands, and administrative commands, into submission queues that are implemented in host memory). However, Benisty does not appear to expressly teach while:
Malwankar discloses: “storing the data in the buffer.” (e.g., Fig. 5, col. 19, lines 14-26, At block 515, processing logic retrieves the data block associated with the logical address from the buffer. At block 520, processing logic returns a response to the read request received at block 505 with the data block retrieved from the buffer).
20. Regarding claim 20 Bemist further teaches:
“wherein the device is configured to process the request in the entry of the queue and a second request in a second entry of the queue according to an interval.” (e.g., Fig. 14, col. 18, lines 33-38, if the host device 1402 employs first and second timeout intervals and issues first commands subject to the first timeout internal and second commands subject to the second timeout interval or subject to no timeout interval))
Response to Remarks
Applicant’s Arguments have been fully considered but they are not persuasive.
Page 6 of the Remarks make a reference to ¶ 7.06 and recites any changes in status between 102 and 103 must be considered a change in the ground of rejection. The Examiner interpret the ¶ 7.06 differently. For convenient a copy of the information regarding the ¶ 7.06 (MPEP 2152.07) reproduced as shown below:
“¶ 7.06 Notice re prior art available under both pre-AIA and AIA ”
“In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner Note:
1. This form paragraph must be used in all Office Actions when a prior art rejection is made in an application with an actual filing date on or after March 16, 2013, that claims priority to, or the benefit of, an application filed before March 16, 2013.
2. This form paragraph should only be used ONCE in an Office action.” (Emphasis added).
The paragraph states In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35U.S.C. 102 and 103 ) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The key words or phrase in the event of determination that status … is incorrect, any correction will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Examiner note 1 states that the paragraph must be included in all Office Actions when a prior art rejection is made in an application with an actual filing date on or after March 16, 2013, that claims priority to, or the benefit of, an application filed before March 16, 2013. However, the Paragraph does not recite that the ¶ 7.06 must not be used for the application that does not claim priority to, or the benefit of, an application filed before March 16, 2013.
Regarding the rejection under 35 USC 102, Applicant states:
"Because the hallmark of anticipation is prior invention, the prior art reference - in order to anticipate under 35 U.S.C. § 102 - must not disclose all elements of the claim within the four corners of the document, but must also disclose those elements 'arranged as in the claim”. Applicant make references to some court cases and disagrees with the office action mailed 12/31/2025, which used the disclosure of Benisty (see page 7-8 of the Remarks). However, in view of amendment of claims, the claims are now rejected as being unpatentable under 35 USC § 103 over Benisty in view of Malwankar.
Regarding rejection of the independent claim 11 , page 8 of the Remarks recites:
“In rejecting claim 11, the Office Action argues that Benisty teaches associating, by the processor, the request in the entry of the queue with a buffer in the memory, citing Figure 2 and column 10, lines 15-16 (see Office Action dated December 31, 2025, page 9). The Applicant respectfully disagrees.” (emphasis added).
As has been noted above the buffer is actually appears to be in storage device not in the memory.
Benisty teaches that submission and completion queues, residing in the host memory, may be implemented as circular or ring buffer, page 8 of the Remarks states this argument does not appear to be consistent with the claim and the specification. The Remarks makes a reference to page 17, lines 14-15 of the claimed specification, which for convenience reproduced as shown below:
“Buffers 420 may provide additional storage space for data to be exchanged between processor 110 of FIG. 1 and storage device 120 of FIG. 1” (page 8 of the Remarks, emphasis added).
However, buffers 420 is in the storage device, which inconsistent from the claim limitation that recites, in part, the limitation of:
“placing, by a processor, a request in an entry of a queue in a memory, the memory further including a buffer;“ (emphasis added).
Interpreting the claim in view of the specification, one having ordinary skill in the art, considers the memory 115 shown in Figs. 1 and 2 of the instant application as a memory recited in claim 11. The specification recites memory 115 (e.g., the host memory) is used for temporary storage. The implementation or allocation of memory to queue(s)/buffer(s) appears to take place in the storage device and uses the memory of the storage device. The claimed specification recites (e.g., PGBUP):
“FIG. 3 shows how storage device 120 of FIG. 1 may use a ring buffer for streaming operations, according to embodiments of the disclosure. In FIG. 3, ring buffer 305 is shown. Ring buffer 305 may be a queue that is circular…” (e.g., par. 0042 of the spec., emphasis added).
“FIG. 4 shows details of entry 310 of FIG. 3, according to embodiments of the disclosure. In FIG. 4, entry 310 is shown in greater detail…” (e.g., par. 0065 of the spec., emphasis added).
It appears to be discrepancy/inconsistency between what is claimed and description/definition in the spec.
Benisty teaches that exchange/transfer of commands including data and status, between host and storage, take place Via a plurality of queues using circular or ring buffers (e.g., see col. 1, lines 40-55). The submission queues are initially used to store commands and data provided by the host processor and be transmitted to storage device. The completion queue used to store or post completion status result of memory operations performed by the storage controller. When request is for reading/retrieving data from storage device, the read data is transferred by the storge controller to the host (e.g., the host memory, the host memory includes additional buffers 708, Fig. 7).
Benisty further teaches the storage device controller may throttle of insertion commands by the host to avoid timeout. The throttling comprises adjusting or changing head pointer (e.g., in circular buffer). Page 8 of the Remarks recites that size of completion queue for storing data 16 bytes according to col. 11, line 36 of Benisty). The entries are or slot size indicated for storing status of the completed command). Furthermore, Applicant also argues subject matters that is not in the claim. The circular queue entry or slot size is not included claim 11.
Column 1, lines 15-40 of Benisty refers to the NVM Express standard, which defines the function submission and completion queues and the manner in which command, data, and status exchanged between the host and storage system. It describe an example of read command for a 64 KB data. The storage controller transfers read data to the host (memory) and after completion, post the status of storage operations into the Completion queue.
In view amendment, independent clams 11,16, and claims depending from claims 11 and 16 are rejected under 35 USC 103 as being unpatentable over Bemists in view of Malwankar. Regarding rejection of independent claim 16. The claim recites the limitation “processing, by the device, the request using at least one of the device and a buffer in the memory”, On page 10 of office action mailed 12/31/2025, references made to Fig. 5, col. 11, lines 10-42 and Fig. 6, lines 43-67. Column associated with lines 43-67 unintentionally excluded. Since column was not indicated, the Remarks recites perhaps column 6 is the excluded column (see page 12 of the Remarks). However, the portion of Benisty spec. related to Fig. 6 and lines 43-67, is column 11. Furthermore, the office action described the subject matter associated to both Figs. 5 and 6. The Remarks appears to discard portion related to Fig. 5 and submission queue and thus is not responsive to the all elements of office action.
As has been noted above with respond to arguments regarding claim 11 and also described in Colum 11 related to Figs.5-6 of Benisty, the host memory comprises submission and completion queues implemented circular or ring buffers. Host store write commands, comprising write data, to submission queue(s). The device controller fetches the command from the submission queue, executes the commands, and stores status of completion into the host completion queue. In case of read command, the read data associated with read commands are delivered to the host memory (e.g., buffers) As noted above, claim 11 rejected under 103, obviousness. Malwankar teaches that data is read from a buffer.
The independent claim 16 includes similar limitations, and the response to arguments regarding claim 11 would apply.
Claim 12 is rejected as being unpatentable over Benisty and Malwankar. Malwankar teaches that reading the data from a buffer.
Claim 13 is rejected as being unpatentable over Benisty in view of Malwankar. The combinations teach or render obvious the limitation(s) recited in the claim. There are queues in memory implemented as ring buffers. Specification does not describe allocating queue in memory.
Regarding claim 14, Benisty in view of Malwankar teach notifying the storage device.
Regarding claim 15 Benisty teaches throttling to set or adjust timeout interval. The timeout is for the host issuing command stored in the circular buffer.
Regarding claim 16, as has been noted above, claim 16 recite substantially the same limitations as claim 11. Response to the arguments regarding claim 11 would apply.
Regarding claim 17, Benisty teaches status commands(e.g., completion, set or cleared). Status of command updated in field or entry of the completion queue in a circular buffer.
Regarding claim 19, combination of Benisty and Malwankar teach or render obvious all limitation(s) recited in claim 19.
Regarding claim 20, Benisty teaches throttling used to set or adjust timeout interval for the host issuing commands. This limitation is also taught by Malwankar (e.g., see col. 1, line 62 to col. 2, line 14 of Malwankar).
Regarding claim 1, combination of Benisty and Malwankar teach or render obvious all limitation(s) recited in claim. Applicant appears to agree that Benisty teaches submission and completion queues are circular or ring buffers. But states this arguments does not appear to be consistent with the claim and the specification. For example, the specification states that "[b]uffers 420 may provide additional storage space for data to be exchanged between processor 110 of FIG. 1 and storage device 120 of FIG. 1" (see specification, page 17, lines 14-15). Claim 1 recites, in part the limitation:
“the memory including a queue and a buffer, the queue including an entry, the buffer identified by the entry;” (emphasis added).
The buffers 420 reside in the storage device not the memory. It appears the claim limitation and the arguments are not consistent with the specification. As previously described the host comprises submission queues implemented in circular buffers storing commands issued by the processor. The write command includes write data. Write command is being transferred to storage device to store the write data in storage (e.g., storage array 712 of NVMe device 710, Fig. 7 of Benisty). After completion, the status of write operation is stored in the completion queue. If the request is read command for retrieving read data from the storage device (e.g., NVMe), the read command is transferred to the storage device. After execution and completion read processes, the read data is transferred host memory comprising buffers and status of read operation is stored in the completion queue. Since queue may store a plurality commands, the queues must have a plurality entries with each entry associated with a command. The entry is used to identify the command. Fig. 6 of Benisty shows an example of an entry of completion queue data structure. It provide SQ identifier. Command identifier, and SQ head pointer identifiers among other parameters. In case of read request, the read data is transferred to host memory (e.g., buffers 706 in Fig. 7 of Benisty). However, the status read completion operations with identifiers (e.g., similar to the entry shown in Fig. 6) is recorded in the completion queue to notify the status of read operation associated with the read command).
However, in the office action mailed 12/31/2025, the disclosure of Malwankar used to more directly or additionally teach the limitation. The Examiner respectfully submits the combination Benisty and Malwankar teach or render obvious all limitations included in the claim 1.
Regarding claims 5-7 and 9, Benisty teaches sizes but may not recite size values as recited in the claims. In addition, NVMe standard gives some guidance regarding data size and number of queues (e.g., see col. 1, lines 15-40; col. 9, line 47 to col. 10, line 7).
The memory or portions of are often allocated/deallocated to queues or buffers. Setting a size value(s) definitely is design choice.
Regarding claim 18, Benisty in view of Malwankar teach or render obvious all limitations including identifying buffer.
In summary, the Examiner respectfully submits the combination of Benisty and Malwankar teach or render obvious all limitations included in the claims. Accordingly, the Examiner maintains his position.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see htto://pair-direct.uspto.gov. For questions regarding access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000.
/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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