DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on October 24, 2024 has been considered by the examiner.
Election/Restrictions
The Response to Restriction Requirement has been entered. Claims 1-20 remain pending in this application. Claims 18-19 drawn to non-elected invention have been withdrawn. No claims have been amended. No claims have been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 7-8, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0169527 A1 to Katsuhiro Kitagawa (hereafter Kitigawa) in view of US 8198930 B2 to Jared Zerbe, et al. (hereafter Zerbe).
Regarding Independent Claim 1, Kitigawa discloses a clock signal driver, comprising:
a driver circuit (Delay Locked Loop circuit 100: Kitigawa, ¶[0028]) configured to generate an output clock signal (Generating an internal clock signal LCLK: Kitigawa, ¶[0028]) in response to
an input clock signal (External clock signal CK transformed to internal clock signal ICLK: Kitigawa, ¶[0028]),
a delay control signal (Control Circuit 140 sets the delay amount of delay line 110, indicating the presence of a delay control signal: Kitigawa, ¶[0040]),
said driver circuit comprising:
a main driver circuit (Main DLL circuit 100: Kitigawa, Figure 1)
configured to generate the output clock signal in response to the input clock signal (DLL 100 outputting internal clock signal LCLK from internal clock signal ICLK: Kitigawa, ¶[0037]); and
a replica circuit (Replica driver 120: Kitigawa, ¶[0036]) having a structure equivalent to the main driver circuit (Replica driver 120 being a replica circuit of the output driver: Kitigawa, ¶[0038]),
said replica circuit configured to generate a replica clock signal (Replica driver 120 configured to generate a replica clock signal RepCLK: Kitigawa, ¶[0038]),
which is equivalent to the output clock signal (Equivalent to the output clock signal: Kitigawa, ¶[0038]),
in response to the input clock signal (In response to input clock signal: Kitigawa, ¶[0038]); and
a delay control circuit (Delay control circuit 110: Kitigawa, Figure 2) responsive to the replica clock signal,
said delay control circuit configured to generate the delay control signal (The delay circuit generating the output clock signal: Kitigawa, Figure 2)
to correct a delay change in the output clock signal (Adjusting the output clock signal to correct for variations: Kitigawa, ¶[0039]),
which is caused by a change in voltage level of the power supply voltage (Variations in clock signal caused by variations in the power supply: Kitigawa, ¶[0039]).
Kitigawa suggests providing a power supply voltage, but expressly omits the illustration thereof in the Figures and written detail description (A power supply voltage is implied in the Delay Locked Loop circuit although the illustration thereof is omitted: Kitigawa, ¶[0027]). Zerbe, however, expressly discloses a power supply voltage applied to the driver circuit (Power supply 108: Zerbe, Figure 1). Zerbe teaches the inclusion of a power supply voltage is inherent in a clock buffer chain (Zerbe, col.3:20-23). It would have been necessary, and therefore obvious, to one having ordinary skill in the art, before the effective filing date of this application, to combine the explicit power supply of Zerbe in the circuit as is only implied in Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of Delay Locked Loop clock circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Zerbe discloses the clock signal driver of Claim 1, wherein
the delay control circuit is powered by a first voltage (Replacing VDD with V_ref: Zerbe, col.10:15-17),
which is different from the power supply voltage (V_ref being independent of VDD: Zerbe, col.10:17-19) and
has a constant voltage level (V_ref having a constant voltage level: Zerbe, col.10:17-19).
Regarding Claim 7, Kitigawa discloses the clock signal driver of Claim 1, wherein the driver circuit further includes:
a control circuit (Control Circuit 140: Kitigawa, Figure 2) configured
to receive the input clock signal (Receiving input clock signal ICLK: Kitigawa, Figure 2), and
to generate a first clock signal (Generating an intermediate signal: Kitigawa, Figure 2)
by adjusting a phase or a delay of the input clock signal (Incorporating a phase determination: Kitigawa, Figure 2); and
a main driver (Main driver 100: Kitigawa, Figure 2) operating circuit configured
to generate a second clock signal (Generating an output clock signal LCLK: Kitigawa, Figure 2)
in response to the first clock signal and the delay control signal (In response to the first clock signal and a delay: Kitigawa, Figure 2); and
wherein
the main driver circuit is configured to generate the output clock signal based on the second clock signal (The main driver generating the output clock signal based on internal clock signals: Kitigawa, Figure 2), and
the replica circuit is configured to generate the replica clock signal based on the second clock signal (A replica circuit configured to generate a clock signal based on the prior input: Kitigawa, Figure 2).
Regarding Claim 8, Kitigawa discloses the clock signal driver of Claim 7, wherein the delay control signal includes
a trimming code applied to the main driver operating circuit to correct the delay change in the output clock signal (Delay adjustment including both a coarse and fine timing adjustment: Kitigawa, ¶[0037]).
Regarding Claim 15, Kitigawa discloses the clock signal driver of Claim 7, wherein the control circuit includes:
a receiving circuit configured to receive and amplify the input clock signal (Receiver propagating, and thus enhancing, the clock signal: Kitigawa, ¶[0051]);
a clock tree circuit configured to correct a delay difference depending on a transmission path of the input clock signal (The clock tree adjusting the input clock signal: Kitigawa, ¶[0061]); and
a phase locked loop configured to lock a phase of the input clock signal (The delayed clock circuit phase locked to the input clock signal: Kitigawa, ¶[0061]).
Regarding Claim 16, Kitigawa discloses the clock signal driver of Claim 15, wherein
the receiving circuit includes a plurality of buffers configured to amplify the input clock signal (Receiver propagating, and thus enhancing, the clock signal: Kitigawa, ¶[0051]).
Regarding Claim 17, Kitigawa discloses the clock signal driver of Claim 15, wherein
the first clock signal is generated based on one of the clock tree circuit and the phase locked loop (The phases and timing of the internal clock signal taking the clock tree and delay into account: Kitigawa, ¶[0061]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0169527 A1 to Katsuhiro Kitagawa (hereafter Kitigawa) and US 8198930 B2 to Jared Zerbe, et al. (hereafter Zerbe) in view of US 2011/0102073 A1 to Yoshiro Riho (hereafter Riho).
Regarding Claim 3, Kitigawa discloses the clock signal driver of Claim 1, wherein the delay control signal
is generated by delay control circuit (Generating a delay amount to be used to modify the base clock signal: Kitigawa, ¶[0039]) and
in response to the replica clock signal (Driven by the RepCLK signal: Kitigawa, ¶[0039]),.
during a test of the clock signal driver (The test being performed in the clock signal driver: Kitigawa, ¶[0039]).
Kitigawa discloses adjusting the output clock signal in response to the output of the replica clock signal, but suggests doing this calibration in close to real time (Kitigawa, ¶[0039]), not during wafer level testing. Riho, however, discloses performing a calibration test using replica circuits not used in ordinary circuit operations at the wafer level (Performing a wafer level calibration test: Riho, Figure 4A and Riho, ¶[0079]). Riho teaches performing calibration using a replica circuit can be used to determine precise calibration data with the same characteristics of the real circuit in standard operation. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the wafer level replica calibration testing of Riho with the replica clock circuit of Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of semiconductor memory circuit calibration and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0169527 A1 to Katsuhiro Kitagawa (hereafter Kitigawa) and US 8,198,930 B2 to Jared Zerbe, et al. (hereafter Zerbe) in view of US 2018/0004429 A1 to Kyeong Min Chae (hereafter Chae).
Regarding Claim 4, Kitigawa discloses the clock signal driver of Claim 1, but fails to disclose the further limitations of Claim 4. Chae, however, discloses a clock signal driver wherein the delay control circuit includes:
a flip-flop (D type flip-flop: Chae, ¶[0148]) configured to output a result signal (Configured to output a control clock signal: Chae, ¶[0148])
in response to the replica clock signal and a unit pulse signal (Generating the output clock signal in response to a clock signal, SET_H/SET_L pulse signals, and delay signal: Chae, ¶[0148]); and
a logic calculating circuit configured to generate:
(i) the unit pulse signal as feedback to the flip-flop, and (ii) the delay control signal based on the result signal (Generating the output clock signal in response to a clock signal, SET_H/SET_L pulse signals, and delay signal: Chae, ¶[0148]).
Chae teaches these types of circuits may improve the operating speed of a memory device (Chae, ¶[0011]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the speed circuit of Chae with the replica clock circuit of Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of efficient memory circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 6, Chae discloses the clock signal driver of Claim 4, wherein the unit pulse signal
has an activation time interval corresponding to 1 unit interval (UI) of data that is input to and output from a memory device operating based on the output clock signal (The data transmit signal being synchronized to the clock signal: Chae, ¶[0046]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0169527 A1 to Katsuhiro Kitagawa (hereafter Kitigawa), US 8,198,930 B2 to Jared Zerbe, et al. (hereafter Zerbe), and US 2018/0004429 A1 to Kyeong Min Chae (hereafter Chae) in view of US 6,622,103 B1 to Charles A. Miller (hereafter Miller).
Regarding Claim 5, Kitigawa discloses the clock signal driver of Claim 4, but fails to disclose the further limitations of Claim 5. Miller, however, discloses a circuit:
wherein the logic calculating circuit (Timing calibration circuits: Miller, col.7:56) is configured
to store a plurality of first time points that occur while changing the voltage level of the power supply voltage (Sampling the signals at regular time points: Miller, col.9:10-15), and
to generate the delay control signal based on the plurality of first time points (To iteratively determine the appropriate delay signal: Miller, col.9:33-37); and
wherein the plurality of first time points indicate time points when the result signal transitions between logic levels (Wherein the delay is relative to the signal change edge: Miller, col.9:48-51).
Miller discloses this method of calibration better accounts for time delays through the interconnect system (Miller, col.8:30-35). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the precise time delay measurement methods of Miller with the replica clock delay method of Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of memory circuit calibration and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0169527 A1 to Katsuhiro Kitagawa (hereafter Kitigawa) and US 8198930 B2 to Jared Zerbe, et al. (hereafter Zerbe) in view of US 7,603,094 B2 to Mahibur Rahman (hereafter Rahman).
Regarding Claim 9, Kitigawa discloses the clock signal driver of Claim 8, but fails to disclose the further limitations of Claim 9. Rahman, however, discloses a clock signal driver:
wherein the delay control signal (Delay stage signal: Rahman, col.10:44-46) further includes
a register signal for changing a device setting value of the driver circuit to additionally correct the delay change in the output clock signal (The register signal changing a device setting: Rahman, col.10:52-55); and
wherein the device setting value includes
a gain of the control circuit (Device setting including gain: Rahman, col.10:54-55),
an intensity of a current flowing through the control circuit (Current offset: Rahman, col.2:64-65) and
a transistor strength of the main driver circuit (Transistor settings: Rahman, col.6:45-47).
Rahman teaches this circuit configuration allows for updates within a closed system to account for environmental variations (Rahman, col. 10:23-28). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the register signal controls of Rahman with the replica clock circuit of Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of clock signal delay calibration for memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0169527 A1 to Katsuhiro Kitagawa (hereafter Kitigawa) and US 8198930 B2 to Jared Zerbe, et al. (hereafter Zerbe) in view of US 10749481 B2 to Bo Sun, et al. (hereafter Sun).
Regarding Claim 10, Kitigawa discloses the clock signal driver of Claim 7, but fails to disclose the further limitations of Claim 10. Sun, however, disclose a clock signal driver wherein the main driver operating circuit includes:
a pre-driver circuit configured to amplify the first clock signal (A driver in a circuit: Sun, col.1:29-33); and
a delay cell circuit (Delay circuit: Sun, col. 3:45-47) configured to correct the delay change in the output clock signal that occurs in response to changes in the voltage level of the power supply voltage (The delay being configured to compensate for variations in supply voltage: Sun, col.4:20-41).
Sun teaches the use of variable resistors and capacitors in a delay circuit allows the resultant delay to increase with supply voltage, whereas delay would normally decrease as voltage increases (Sun, col.3:67-4:4). Increasing the delay correspondingly with voltage helps reduce signal jitter (Sun, col.3:54-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the jitter reducing voltage-corresponding-delay of Sun with the replica clock circuitry of Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of clock signal delay calibration and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 11, Sun discloses the clock signal driver of Claim 10,
wherein the pre-driver circuit includes a plurality of inverters connected in series (A series of inverters in a pre-driver circuit is routine in the industry) ; and
wherein the delay cell circuit includes
a plurality of variable resistors (Delay circuit including variable resistors: Sun, col.4:20-41) and
a plurality of variable capacitors (Delay circuit including variable capacitors: Sun, col.4:20-41)
that are connected to the plurality of inverters (The variable components modifying the delay signal: Sun, col.4:20-41).
Regarding Claim 12, Sun discloses the clock signal driver of Claim 11,
wherein the plurality of inverters include
a first inverter and a second inverter (First inverter Mn1 and second inverter Mn2: Sun, Figure 5), and
an input of the first inverter and an output of the second inverter are connected to a first node (Output of Mn2 and input to Mn1 connected to a central node: Sun, Figure 5);
wherein the plurality of variable resistors include a first variable resistor (A plurality of variable resistors will inherently include a first variable resistor), and
the plurality of variable capacitors include a first variable capacitor (A plurality of variable capacitors will inherently include a first variable capacitor); and
wherein the first variable resistor and the first variable capacitor are connected in series between the first node and a ground voltage (The variable resistor and variable capacitor connected in series between the node and ground voltage: Sun, Figure 2B).
Regarding Claim 13, Sun discloses the clock signal driver of Claim 10, but fails to disclose the further limitations of Claim 13. Houghton, however, discloses a delay circuit wherein the delay cell circuit is configured to
apply a delay that increases as the voltage level of the power supply voltage increases to the first clock signal (Disclosing a delay circuit wherein delay decreases as voltage level decreases: Sun, col.3:66-4:4).
Regarding Claim 14, Houghton discloses the clock signal driver of Claim 10, wherein the delay cell circuit is configured to
apply a delay that increases linearly in proportion to the voltage level of the power voltage to the first clock signal (Disclosing a delay circuit wherein delay tracks the voltage level: Sun, col.3:66-4:4).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0169527 A1 to Katsuhiro Kitagawa (hereafter Kitigawa) in view of US 8198930 B2 to Jared Zerbe, et al. (hereafter Zerbe), US 2018/0004429 A1 to Kyeong Min Chae (hereafter Chae), and US 10749481 B2 to Bo Sun, et al. (hereafter Sun).
Regarding Independent Claim 20, Kitigawa discloses a clock signal driver, comprising:
a driver circuit (Delay Locked Loop circuit 100: Kitigawa, ¶[0028]), and
to generate an output clock signal (Generating an internal clock signal LCLK: Kitigawa, ¶[0028]) in response to an input clock signal (External clock signal CK transformed to internal clock signal ICLK: Kitigawa, ¶[0028]) and
a delay control signal (Control Circuit 140 sets the delay amount of delay line 110, indicating the presence of a delay control signal: Kitigawa, ¶[0040]),
the driver circuit comprising:
a control circuit configured to receive the input clock signal (Control circuit configured to receive an input clock signal: Kitigawa, Figure 1), and
to generate a first clock signal by adjusting a phase or a delay of the input clock signal (Generating a delay amount to be used to modify the base clock signal: Kitigawa, ¶[0039]);
a main driver operating circuit configured to generate a second clock signal in response to the first clock signal (Operating circuit generating an internal clock signal based on a primary clock signal: Kitigawa, ¶[0028]) and the delay control signal (And incorporating a delay signal: Kitigawa, ¶[0037]);
a main driver circuit (Main DLL circuit 100: Kitigawa, Figure 1) configured to generate the output clock signal in response to the second clock signal (DLL 100 outputting internal clock signal LCLK from internal clock signal ICLK: Kitigawa, ¶[0037]); and
a replica circuit (Replica driver 120: Kitigawa, ¶[0036]) having a same structure as the main driver circuit (Replica driver 120 being a replica circuit of the output driver: Kitigawa, ¶[0038]), and configured to generate a replica clock signal (Replica driver 120 configured to generate a replica clock signal RepCLK: Kitigawa, ¶[0038]) identical to the output clock signal (Equivalent to the output clock signal: Kitigawa, ¶[0038]).
Kitigawa suggests providing a power supply voltage, but expressly omits the illustration thereof in the Figures and written detail description (A power supply voltage is implied in the Delay Locked Loop circuit although the illustration thereof is omitted: Kitigawa, ¶[0027]). It also fails to disclose the delay control circuit being configured to operate based on a first voltage that is different from the power supply voltage and has a constant voltage level.
Zerbe, however, discloses a driver circuit including:
configured to operate based on a power supply voltage (Power supply 108: Zerbe, Figure 1)
a delay control circuit configured to operate based on a first voltage (Replacing VDD with V_ref: Zerbe, col.10:15-17) that is different from the power supply voltage (V_ref being independent of VDD: Zerbe, col.10:17-19) and has a constant voltage level (V_ref having a constant voltage level: Zerbe, col.10:17-19),
Zerbe teaches the inclusion of a power supply voltage is inherent in a clock buffer chain (Zerbe, col.3:20-23). Therefore, it would have been necessary, and therefore obvious, to one having ordinary skill in the art, before the effective filing date of this application, to combine the explicit power supply of Zerbe in the circuit as is only implied in Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of Delay Locked Loop clock circuits and the combination of known inventions with predictable results is obvious and not patentable.
Kitigawa fails to disclose the delay control circuit comprising a flip-flop configured to output a result signal in response to a replica clock, nor a logic calculating circuit configured to generate the unit pulse signal, as described. Chae, however, discloses a delay control circuit comprising:
a flip-flop (D type flip-flop: Chae, ¶[0148]) configured to output a result signal (Configured to output a control clock signal: Chae, ¶[0148]) in response to the replica clock signal and a unit pulse signal (Generating the output clock signal in response to a clock signal, SET_H/SET_L pulse signals, and delay signal: Chae, ¶[0148]); and
a logic calculating circuit configured to generate the unit pulse signal, and to generate the delay control signal for correcting a delay change in the output clock signal in response to the result signal (Generating the output clock signal in response to a clock signal, SET_H/SET_L pulse signals, and delay signal: Chae, ¶[0148]).
Chae teaches these types of circuits may improve the operating speed of a memory device (Chae, ¶[0011]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the speed circuit of Chae with the replica clock circuit of Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of efficient memory circuits and the combination of known inventions with predictable results is obvious and not patentable.
Kitigawa does not teach the delay change in the output clock signal occurring in response to a change in a voltage level of the power supply voltage. Sun, however teaches the delay change in the output clock signal occurring in response to a change in a voltage level of the power supply voltage (Disclosing a delay circuit wherein delay decreases as voltage level decreases: Sun, col.3:66-4:4).
Sun teaches the use of variable resistors and capacitors in a delay circuit allows the resultant delay to increase with supply voltage, whereas delay would normally decrease as voltage increases (Sun, col.3:67-4:4). Increasing the delay correspondingly with voltage helps reduce signal jitter (Sun, col.3:54-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the jitter reducing voltage-corresponding-delay of Sun with the replica clock circuitry of Kitigawa, with a reasonable expectation of success. Both inventions are well known in the field of clock signal delay calibration and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5,532,969 A to Russell J. Houghton et al.: Teaching a delay circuit configured to increase the delay proportionally to the supply voltage.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824
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