CTNF 18/925,469 CTNF 91599 Detailed Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 2-10, 12-19, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirai [20150062626], in view of Fung [20070240006] As to claim 2, Hirai [20150062626] teaches A computer-implemented method of controlling power consumption in a multi-processor computing device, the method comprising: managing control rules for associated with a first processor [ 0010: “managing a power control rule for a change of a state of the one or more information processing devices ”]; determining one or more power settings for the first processor based on the first set of control rules [0010: “ determining, based on the information obtained in the obtaining step, whether or not the power control ability of the information processing device matches the power control rule managed in the managing step ”]; and causing the first processor to perform one or more operations based on the one or more power settings [0010: “ setting the power control rule managed in the managing step to the information processing device if it has been determined that the power control ability of the information processing device matches the managed power control rule, and setting a new power control rule that matches the power control ability of the information processing device ”]. But does not explicitly teach selecting a first set of control rules for determining workload pulsing parameter settings However Fung [20070240006 ] teaches selecting a first set of control rules for determining workload pulsing parameter settings [299: “ A system as in embodiment (3), wherein when there is a requirement that one computer be placed in a lower power consumption mode, the computer selected for such lower power consumption is selected according to predetermined rules such that different computers are placed in lower power consumption mode each time such selection is required. ” and 299: “ A system as in embodiment (60), wherein the detection of execution of an idle thread initiated power reduction provides a real time adjustment to power consumption based on measured processor load requirements . (77) A system as in embodiment (57), wherein the QoS initiated power reduction provides a preset adjustment to power consumption based on predicted processor load requirements. (78) A system as in embodiment (57), wherein the QoS requirement is adjusted on at least one of a time-of-day criteria, a day-of-week criteria, a seasonal criteria, and combinations thereof. (79) A system as in embodiment (57), wherein the QoS requirement is adjusted based on criteria selected from the set consisting of: time-of-day, day-of-month, day-of week, month-of year, geographic location of requester, requester identity, requester account number, and combinations thereof. (80) The computer system in embodiment (3), wherein the activity indicator comprises a network quality of service indicator. ”And 299: “ A system as in embodiment (3), wherein a quality-of-service (QoS) is first established, and a processor performance is established based on predetermined policies that select a processor clock frequency, and a minimum processor core voltage is selected to match the selected processor clock frequency ; and wherein the established processor performance is used to control an operating mode. (68) ”] It would have been obvious to person of ordinary skill in the art before the effective filing date of the claimed invention to combine teaching of Hirai and Fung teach because both are directed toward power change. Furthermore, Fung improves upon Hirai by being able to select a power change based on predetermined and selected rules such that device can be in exact power setting for efficient power state change. As to claim 3, Fung teaches comprising, prior to selecting the first set of control rules, determining that a workload of the first processor comprises a frame-based workload [304: “An information processing system comprising: a frame or enclosure for mounting a plurality of devices; a backplane having a plurality of backplane electrical connectors disposed within the frame or enclosure; and a plurality of devices, each including a device electrical connector, matingly coupled to the backplane electrical connectors, the plurality of devices including at least one network device for coupling the system with an external network. ”]. As to claim 4, Fung teaches determining the one or more power settings for the first processor includes selecting a fixed operating voltage for the first processor during workload pulsing[0305: “ An information processing system comprising: a frame or enclosure for mounting a plurality of devices; a backplane having a plurality of backplane electrical connectors disposed within the frame or enclosure; and a plurality of devices, each including a device electrical connector, matingly coupled to the backplane electrical connectors, the plurality of devices including at least one network device for coupling the system with an external network.”]. As to claim 5, Fung teaches the fixed operating voltage is a lowest operating voltage for the first processor[ 299: “A system as in embodiment (3), wherein when there is a requirement that one computer be placed in a lower power consumption mode , the computer selected for such lower power consumption is selected according to predetermined rules such that different computers are placed in lower power consumption mode each time such selection is required. ”]. As to claim 6, Fung teaches determining the one or more power settings for the first processor includes selecting a fixed operating frequency for the first processor during workload pulsing [0239: “One of the Transmeta Crusoe Model chips operates at 533 MHz and 1.6 volts when in Mode 1 and at 300 MHz and 1.2 volts when at its slowest CPU clock frequency and lowest CPU core voltage in Mode 2.”]. As to claim 7, Fung teaches the fixed operating frequency is a highest operating frequency for the first processor while the first processor operates at a specific operating voltage [0188: “It is initially assumed that the system is operating in Mode 1 having the highest processor unit (e.g. CPU) performance level and greatest power consumption of the available operating modes. ”]. As to claim 8, Fung teaches the workload pulsing parameter settings include at least one of an idle state duration, a workload pulse duration, a frame-rate limit, or a maximum work-issue rate [0063: “Those node resources that are not needed may be powered off or placed i n some power conserving standby mode until needed. In addition, operations performed by one or more nodes may be shifted to another node so that only the remaining active nodes consume power and the remaining nodes are in standby mode or powered off until needed. The intelligence within one of the nodes acting as a master node for the cluster or ISS may then wake up the inactive node and configure it for operation. A system may be woken up and placed in any of the available operating modes by any one of a plurality of events”]. As to claim 9, Fung teaches comprising, prior to selecting the first set of control rules, determining that the first processor is operating in a low-power regime [0172: “The structures and methods of the invention provides a very low power design so that even when the inventive server is operating at its maximum performance level and consuming its maximum power, that maximum power consumption is still a fraction of the maximum (and steady-state) power consumption of conventional non-power managed processors and servers. This maximum power level is typically between about 10 to 15 Watts though it may fall within other ranges or be reduced further. This reduction is possible for several reasons, including the provision of a very low power consumption processor or CPU, turning off devices or components within the system that are not being used at the time.”]. As to claim 10, Fung teaches determining that the first processor is operating in the low-power regime is based on a power level associated with the first processor [0172: “Another significant power savings is provided by power managing the CPU according to the network traffic or server load conditions. Therefore, the power consumption is less than the maximum power consumption unless the load is at a peak and all of the devices and components are powered on to handle the load. With this throttling back as a function of load, the power consumption may be at any intermediate value between zero (when and if the unit is powered off completely) or at a very low power consumption level when placed in some power conserving mode (such as a sleep, suspend, or other specialized power conserving mode as described elsewhere herein). ”]. As to claim 12-19, Combination of Hirai and Fung teach this claim according to the reasoning set forth in claim 2-9 supra. As to claim 21, Combination of Hirai and Fung teach this claim according to the reasoning set forth in claim 2 supra . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 11, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571) 270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KESHAB R PANDEY/Primary Examiner, Art Unit 2176 Application/Control Number: 18/925,469 Page 2 Art Unit: 2176 Application/Control Number: 18/925,469 Page 3 Art Unit: 2176 Application/Control Number: 18/925,469 Page 4 Art Unit: 2176 Application/Control Number: 18/925,469 Page 5 Art Unit: 2176 Application/Control Number: 18/925,469 Page 6 Art Unit: 2176 Application/Control Number: 18/925,469 Page 7 Art Unit: 2176 Application/Control Number: 18/925,469 Page 8 Art Unit: 2176 Application/Control Number: 18/925,469 Page 9 Art Unit: 2176 Application/Control Number: 18/925,469 Page 10 Art Unit: 2176
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