DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of Patent number: US 12,148,389. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 1 limitations are taught by claim 4 limitations of Patent number: US 12,148,389. However, Patent number: US 12,148,389 does not show the limitations of a third capacitor connected between the third power input terminal and the fourth node, wherein a drain of the seventh transistor and a drain of the eighth transistor are connected to the output terminal forming a node with a gate line, a drain of the seventh transistor is connected to the second power input terminal, and a source of the eighth transistor is connected to the third power input terminal.
In related art, Park et al shows the limitations of a third capacitor connected between the third power input terminal and the fourth node, wherein a drain of the seventh transistor and a drain of the eighth transistor are connected to the output terminal forming a node with a gate line, a drain of the seventh transistor is connected to the second power input terminal, and a source of the eighth transistor is connected to the third power input terminal (see figure 7A; paragraphs 126 and 127).
Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the application to incorporate the teaching of park et al into the teaching of CAI in order to compensate threshold voltage (see Park et al; paragraphs 126 and 127).
18/925,558 (Current Application)
Patent number: US 12,148,389
1. A gate driver comprising a plurality of stages, each of the plurality of stages comprising: an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node; a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node; an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal; a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node; and a third capacitor connected between the third power input terminal and the fourth node, wherein a drain of the seventh transistor and a drain of the eighth transistor are connected to the output terminal forming a node with a gate line, a drain of the seventh transistor is connected to the second power input terminal, and a source of the eighth transistor is connected to the third power input terminal.
4. A gate driver comprising a plurality of stages, each of the plurality of stages comprising: an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node; a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node; a ninth transistor, the ninth transistor including one electrode connected to the fourth node and a gate electrode connected to a third input terminal receiving a second clock signal; a tenth transistor connected between the ninth transistor and the third input terminal, the tenth transistor including a gate electrode connected to a fifth node; an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal; a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node; a thirteenth transistor connected between a second node and the fifth node, the thirteenth transistor including a gate electrode connected to a first power input terminal; and a third capacitor connected between the third power input terminal and the fourth node
Allowable Subject Matter
Claim 1 would be allowed if Applicant overcomes the Double Patenting rejection.
The following is an examiner’s statement of reasons for allowance: The best prior art of record, i.e., CAI (Publication number: US 2021/0327337) in view of Park et al (Publication number: US 2020/0394984) do not specifically show the limitations of “a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node; an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node different from the third power input terminal; a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal different from the third node; and a third capacitor connected between the third power input terminal and the fourth node, wherein a drain of the seventh transistor and a drain of the eighth transistor are connected to the output terminal forming a node with a gate line, a drain of the seventh transistor is connected to the second power input terminal, and a source of the eighth transistor is connected to the third power input terminal.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 06/07/2025
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