DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lal et al (US Publication No. 20200350186) in view of Brcka (US Publication No. 20040233608).
Regarding claim 1, Lal teaches a method of forming an electrostatic chuck (ESC) (i.e., ESC; fig. 4), comprising: forming a plurality of first grooves (i.e., first grooves 157; fig. 3) that are interconnected (i.e., interconnected; para. [0011]) in a lower surface (i.e., lower surface 116; fig. 3) of a ceramic plate (i.e., ceramic plate 120; fig. 3); forming a plurality of second grooves (i.e., second grooves 156; fig. 3) that are interconnected (i.e., interconnected; para. [0011]) in the lower surface of the ceramic plate and that are separate from the plurality of first grooves (i.e., the first grooves/outer grooves 157 is separated from the second grooves/inner grooves 156. Inner groove 156 and outer groove 157 of grooves 155 are further defined by a plurality of arcuate, spaced apart channel portions that zig-zag across the top side 115 of disc 120 in a common plane; para. [0058]); depositing a metal layer (i.e., hard metals such as tungsten or their alloys; para. [0062]) in the plurality of first grooves to form a first electrode (i.e., first electrode 112; fig. 4) and in the plurality of second grooves to form a second electrode (i.e., second electrode 111; fig. 4).
Lal does not teach wherein filling the plurality of first grooves and the plurality of second grooves with a dielectric material.
Brcka teaches in a similar field of endeavor in ESCs; wherein filling the plurality of first grooves (i.e., first grooves 52; fig. 3A) and the plurality of second grooves (i.e., second grooves 52; fig. 3A) with a dielectric material (i.e., dielectric material 34; fig. 3A).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally filled the grooves pattern of the ESC in Lal, as taught by Brcka, as it provides the advantage of optimizing the circuit design towards preventing high-voltage electrical breakdown, maintaining uniform clamping pressure, and ensuring stable thermal cooling across semiconductor wafers.
Regarding claim 2, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Lal further teaches forming a plurality of third grooves (i.e., third grooves 166; fig. 8) that are interconnected (i.e., interconnection; para. [0075]) in the lower surface of the ceramic plate; depositing the metal layer in the plurality of third grooves to form a third electrode (i.e., third electrode 126/129; fig. 10).
Brcka furthermore teaches filling the plurality of third grooves (i.e., third grooves 52; fig. 3A) with the dielectric material (i.e., dielectric material 34; fig. 3A).
Regarding claim 3, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Lal further teaches wherein forming the plurality of first grooves and the plurality of second grooves is performed via saw dicing, laser machining, or ultrasonic machining (i.e., a laser engraving technique may be deployed. Other, similar techniques may be used to fabricate grooves 155,165 without departing from the teachings of the instant disclosure. For example, grooves 155,165 may be formed in the green disc 120 when disc 120 is initially pressed and formed. Alternatively, grooves 155,165 may be machined into disc 120 after initial formation of disc 120; para. [0086]).
Regarding claim 7, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Lal further teaches wherein the metal layer comprises a metallic ink or metallic paste comprising aluminum, titanium, tungsten, molybdenum, platinum, or an alloy thereof (i.e., equivalent compounds of refractory hard metals such as tungsten or their alloys; para. [0062]).
Regarding claim 8, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Lal further teaches wherein at least one of: the ceramic plate has a thickness of about 0.5 mm to about 3.0 mm, or the ceramic plate (e.g., 120) is a sintered plate (i.e., sintering plate/disc 120; para. [0082]).
Regarding claim 10, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Brcka furthermore teaches wherein the dielectric material comprises a silicone paste, polyimide, acrylic, a plasma spray ceramic material, alumina, compounds comprising aluminum or yttrium, or epoxy (i.e., in which alumina (.di-elect cons..sub.r=9.5) is chosen as the dielectric material constituting the planarization dielectric coating 34 and the maximal thickness of the planarization dielectric coating 34 is 1 mm; para. [0063]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lal et al (US Publication No. 20200350186) in view of Brcka (US Publication No. 20040233608) and further in view of Jindo et al (US Publication No. 20150077895).
Regarding claim 4, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Neither Lal nor Brcka wherein bonding a cooling plate made of a metal or metal alloy to the lower surface of the ceramic plate; and bonding a second ceramic plate to the cooling plate.
Jindo teaches in a similar field of endeavor in ESCs wherein bonding (i.e., via bonding layer 40; fig. 2) a cooling plate made of a metal (i.e., metal bonding layer 34; fig. 2) or metal alloy to the lower surface of the ceramic plate (i.e., the bottom face of the ceramic plate 20; fig. 2); and bonding (i.e., via bonding layer 35; fig. 2) a second ceramic plate (i.e., second ceramic plate 33) to the cooling plate (34)(fig. 2).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ECS cooling plate in Lal, as taught by Jindo, as it provides the advantage of optimizing the circuit design towards removing intense heat generated by high-power plasma during semiconductor processing, stabilizing wafer temperatures to prevent structural warping, and ensuring uniform etch or deposition rates across the entire surface to maximize manufacturing yields.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lal et al (US Publication No. 20200350186) in view of Brcka (US Publication No. 20040233608) and further in view of Lue et al (US Patent No. 6264467).
Regarding claim 5, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Neither Lal nor Brcka wherein forming the plurality of first grooves and the plurality of second grooves is performed by depositing a ceramic material on the lower surface of the ceramic plate.
Lue teaches in a similar field of endeavor in ESCs wherein forming the plurality of first grooves (i.e., first grooves between ribs 926; fig. 17) and the plurality of second grooves (i.e., second grooves between ribs 926; fig. 17) is performed by depositing (i.e., deposited by chemical vapor deposition; Col. 9 lines 36+) a ceramic material (i.e., ceramic material 990; fig. 17) on the lower surface of the ceramic plate (i.e., surface 910; fig. 17) (e.g., Coating material 990 can be deposited by chemical vapor deposition, sputtering, or any well-known method. Coating material 990 can preferably be a non-contaminating, semiconducting ceramic or dielectric film such as SiC, SiN, or SiO.sub.2, for example; Col. 9 lines 36+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally deposited the ceramic material in Lal, as taught by Lue, as it provides the advantage of optimizing the circuit design towards protecting underlying metal bases from aggressive plasma, preventing electrical arcing, sealing helium cooling channels, and maintaining uniform thermal transfer across semiconductor wafers.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lal et al (US Publication No. 20200350186) in view of Brcka (US Publication No. 20040233608) and further in view of Wang et al (US Publication No. 20160020128).
Regarding claim 6, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Neither Lal nor Brcka wherein polishing an upper surface of the ceramic plate to make the upper surface able to electrostatically retain a substrate disposed thereon.
Wang teaches in a similar field of endeavor in ESCs wherein polishing an upper surface (i.e., upper surface 21; fig. 1) of the ceramic plate (i.e., 20; fig. 1) to make the upper surface (i.e., 21; fig. 1) able to electrostatically retain (i.e., retains; para. [0018]) a substrate (i.e., wafer W1; fig. 1) disposed thereon (implicit, as seen in fig. 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the polishing process in Lal, as taught by Wang, as it provides the advantage of optimizing the circuit design towards ensuring maximum physical contact with a silicon wafer, which provides uniform clamping forces, precise thermal transfer, and prevention of gas leaks or particle contamination during high-vacuum semiconductor processing.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lal et al (US Publication No. 20200350186) in view of Brcka (US Publication No. 20040233608) and further in view of Lue et al (US Patent No. 5761023).
Regarding claim 9, Lal in view of Brcka and the teachings of Lal as modified by Brcka have been discussed above.
Neither Lal nor Brcka wherein forming a plurality of vacuum holes through the ceramic plate to provide vacuum chucking.
Lue teaches in a similar field of endeavor in ESCs wherein forming a plurality of vacuum holes (i.e., vacuum holes 80; fig. 3) through the ceramic plate (i.e., the ceramic plate 64; fig. 3) to provide vacuum chucking (e.g. In an optional embodiment, vacuum holes 80, which may be lift pin holes, can be used to pump out the gas in the central zone using vacuum line 35 of FIG. 1 to further lower the pressure in the central zone. Optionally, additional vacuum holes could be added; Col. 6 lines 25+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the vacuum holes in Lal, as taught by Lue, as it provides the advantage of optimizing the circuit design towards regulating wafer temperatures during high-energy plasma etching and deposition.
Allowable Subject Matter
Claims 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, Lal in view of Brcka teaches the invention set forth above. However, neither Lal nor Brcka particularly teaches a method of forming a multi-panel ESC, comprising: forming a plurality of ESC panels, wherein forming each ESC panel comprises forming the ESC, and further comprising: electrically connecting the first electrode of each of the plurality of ESC panels; and electrically connecting the second electrode of each of the plurality of ESC panels.
Hence claim 11 will be deemed allowable if rewritten in an independent form.
Claims 12-14 depend on objected claim 11, consequently claims 12-14 will also be deemed allowable.
Claims 15-20 are not elected.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
Prosecution Insights