Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mondello et al. (US Pub # 2024/0211643).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Mondello et al. teach a integrated circuit (IC) comprising: a one-time programmable (OTP) memory storing a plurality of bits (see Fig. 1-9, paragraph 0050, 0052, 0061, 0064, OTP memory 61/64); a plurality of functional circuits; a decoder circuit operable to: read, from said OTP memory, a set of bits of said plurality of bits (see Fig. 1-9, paragraph 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, decoder 41 receives enable bits read from OTP memory 61/64 through registers unit); determine a first design configuration of a plurality of design configurations based on a subset of said set of bits, wherein each design configuration of said plurality of design configurations corresponds to a scenario of usage of said IC and specifies a respective convention on usage of a rest of said set of bits for corresponding features to be realized based on one or more of said plurality of functional circuits; and operate a set of functional circuits of said plurality of functional circuits to realize a first set of features indicated by said rest of said set of bits according to said respective convention corresponding to said first design configuration (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0081, decoder 41 select specific configuration for SoC1/SoC2 using SEL1…SELN ).
Even though Mondello et al. teach enabling / disabling of active peripherals of SoC according to customer request (see paragraph 0005) but silent exclusively about functional circuits. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Mondello et al. where peripheral circuitry include analog / digital peripherals i.e. cores, interface, regulators etc (see paragraph 0034) which would be called functional circuitry in order to improve architecture of SoC devices as it selectively enable / disable peripherals on demand and thus improve power optimization, reduce hacking risk (see paragraph 0002, 0007, 0090).
Regarding claim 2, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Mondell et al. further teach wherein when said subset of said set of bits equals a first value, a first set of bits of said rest of said set of bits indicates whether or not to enable a first functional circuit of said plurality of functional circuits, wherein said decoder circuit enables said first functional circuit if said first set of bits indicate that said first functional circuit is to be enabled and does not enable said first functional circuit otherwise (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0081).
Regarding claim 3, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Mondell et al. further teach, wherein said first value for said subset of said set of bits indicates that said scenario of usage of said IC is a testing scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074).
Regarding claim 4, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Mondell et al. further teach, wherein when said subset of said set of bits equals a second value, a second set of bits of said rest of said set of bits indicates a specific frequency at which a second functional circuit of said plurality of functional circuits is to be operated, wherein said decoder circuit configures said second functional circuit to operate at said specific frequency (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0077).
Regarding claim 5, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Mondell et al. further teach, wherein said second set of bits is set to a first value if shipped to a first customer and to a second value if shipped to a second customer to cause said second functional circuit to be operative with a first frequency for said first customer and with a second frequency for said second customer,wherein said second value for said subset of said set of bits indicates that said scenario of usage of said IC is a customer sampling scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0080).
Regarding claim 6, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Mondell et al. further teach, wherein when said subset equals a third value, a third set of bits of said rest of said set of bits indicates an identifier of a die/wafer on which said IC is fabricated (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069).
Regarding claim 7, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Mondell et al. further teach, wherein said third value for said subset of said set of bits indicates that said scenario of usage of said IC is a production scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074).
Regarding independent claim 8, Mondello et al. teach a decoder circuit operative in an integrated circuit (IC), the decoder circuit operable to: read, from a one-time programmable (OTP) memory contained in said IC (see Fig. 1-9, paragraph 0050, 0052, 0061, 0064, OTP memory 61/64), a set of bits; determine a first design configuration of a plurality of design configurations based on a subset of said set of bits (see Fig. 1-9, paragraph 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, decoder 41 receives enable bits read from OTP memory 61/64 through registers unit), wherein each design configuration of said plurality of design configurations corresponds to a scenario of usage of said IC and specifies a respective convention on usage of a rest of said set of bits for corresponding features to be realized based on one or more of a plurality of functional circuits contained in said IC (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064); and operate a set of functional circuits of said plurality of functional circuits to realize a first set of features indicated by said rest of said set of bits according to said respective convention corresponding to said first design configuration (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0081, decoder 41 select specific configuration for SoC1/SoC2 using SEL1…SELN )..
Even though Mondello et al. teach enabling / disabling of active peripherals of SoC according to customer request (see paragraph 0005) but silent exclusively about functional circuits. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Mondello et al. where peripheral circuitry include analog / digital peripherals i.e. cores, interface, regulators etc (see paragraph 0034) which would be called functional circuitry in order to improve architecture of SoC devices as it selectively enable / disable peripherals on demand and thus improve power optimization, reduce hacking risk (see paragraph 0002, 0007, 0090).
Regarding claim 9, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Mondell et al. further teach, wherein when said subset of said set of bits equals a first value, a first set of bits of said rest of said set of bits indicates whether or not to enable a first functional circuit of said plurality of functional circuits, said decoder circuit further operable to enable said first functional circuit if said first set of bits indicate that said first functional circuit is to be enabled and does not enable said first functional circuit otherwise (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0072).
Regarding claim 10, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Mondell et al. further teach, wherein said first value for said subset of said set of bits indicates that said scenario of usage of said IC is a testing scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076).
Regarding claim 11, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Mondell et al. further teach, wherein when said subset of said set of bits equals a second value, a second set of bits of said rest of said set of bits indicates a specific frequency at which a second functional circuit of said plurality of functional circuits is to be operated,said decoder circuit further operable to configure said second functional circuit to operate at said specific frequency (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0073).
Regarding claim 12, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Mondell et al. further teach, wherein said second set of bits is set to a first value if shipped to a first customer and to a second value if shipped to a second customer to cause said second functional circuit to be operative with a first frequency for said first customer and with a second frequency for said second customer, wherein said second value for said subset of said set of bits indicates that said scenario of usage of said IC is a customer sampling scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069).
Regarding claim 13, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Mondell et al. further teach, wherein when said subset equals a third value, a third set of bits of said rest of said set of bits indicates an identifier of a die/wafer on which said IC is fabricated (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052).
Regarding claim 14, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Mondell et al. further teach, wherein said third value for said subset of said set of bits indicates that said scenario of usage of said IC is a production scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0077).
Regarding independent claim 15, Mondello et al. teach a method implemented in an integrated chip (IC), the method comprising: reading, from a one-time programmable (OTP) memory contained in said IC (see Fig. 1-9, paragraph 0050, 0052, 0061, 0064, OTP memory 61/64), a set of bits; determining a first design configuration of a plurality of design configurations based on a subset of said set of bits (see Fig. 1-9, paragraph 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, decoder 41 receives enable bits read from OTP memory 61/64 through registers unit), wherein each design configuration of said plurality of design configurations corresponds to a scenario of usage of said IC and specifies a respective convention on usage of a rest of said set of bits for corresponding features to be realized based on one or more of a plurality of functional circuits contained in said IC (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074).; and operating a set of functional circuits of said plurality of functional circuits to realize a first set of features indicated by said rest of said set of bits according to said respective convention corresponding to said first design configuration (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0081, decoder 41 select specific configuration for SoC1/SoC2 using SEL1…SELN ).
Even though Mondello et al. teach enabling / disabling of active peripherals of SoC according to customer request (see paragraph 0005) but silent exclusively about functional circuits. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Mondello et al. where peripheral circuitry include analog / digital peripherals i.e. cores, interface, regulators etc (see paragraph 0034) which would be called functional circuitry in order to improve architecture of SoC devices as it selectively enable / disable peripherals on demand and thus improve power optimization, reduce hacking risk (see paragraph 0002, 0007, 0090).
Regarding claim 16, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Mondell et al. further teach, wherein when said subset of said set of bits equals a first value, a first set of bits of said rest of said set of bits indicates whether or not to enable a first functional circuit of said plurality of functional circuits, said method further comprising enabling said first functional circuit if said first set of bits indicate that said first functional circuit is to be enabled and does not enable said first functional circuit otherwise (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0078).
Regarding claim 17, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Mondell et al. further teach, wherein said first value for said subset of said set of bits indicates that said scenario of usage of said IC is a testing scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069).
Regarding claim 18, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Mondell et al. further teach, wherein when said subset of said set of bits equals a second value, a second set of bits of said rest of said set of bits indicates a specific frequency at which a second functional circuit of said plurality of functional circuits is to be operated, said method further comprising configuring said second functional circuit to operate at said specific frequency (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074).
Regarding claim 19, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Mondell et al. further teach, wherein said second set of bits is set to a first value if shipped to a first customer and to a second value if shipped to a second customer to cause said second functional circuit to be operative with a first frequency for said first customer and with a second frequency for said second customer, wherein said second value for said subset of said set of bits indicates that said scenario of usage of said IC is a customer sampling scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0080).
Regarding claim 20, Mondell et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Mondell et al. further teach, wherein when said subset equals a third value, a third set of bits of said rest of said set of bits indicates an identifier of a die/wafer on which said IC is fabricated, wherein said third value for said subset of said set of bits indicates that said scenario of usage of said IC is a production scenario (see Fig. 1-9, paragraph 0010-0011, 0038-0044, 0050, 0052, 0061, 0064, 0069-0074, 0076-0077).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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