Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on an application filed in Japan on October 30, 2023, and receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. It should be noted that in order to effectively benefit from the foreign priority date, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 25, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Electronic Component Incorporating Substrates Connected By Solder Spacers Including A Core Ball And Covering Layer--
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 5, the limitation “a bump that electrically connects the electronic component and the second connection pad” is unclear as to the intended structure relative to prior limitations. Claim 1 establishes that the electronic component is “mounted on the first substrate” and that the second connection pad is included on the second substrate. Furthermore, the spacer member is established as electrically connecting the first connection pad and the second connection pad with no further limitations relating to the electronic component.
Looking to the instant Specification, Applicant provides no broader set up of a bump ((31); Fig. 1, Paragraph [0031]) electrically connecting the electronic component ((30); Fig. 1, Paragraph [0031]) and “the second connection pad” (which in this case must be identified as (P4); Fig. 1, Paragraph [0045]).
Based on the instant Specification, it is the Examiner’s understanding that the claim limitation is directed toward the structure of a bump (31) that electrically connects the electronic component (30) and a second connection pad ((P2); Fig. 1, Paragraph [0031]), wherein (P2) is separate from the second connection pad (P4) established by the claim limitations.
Therefore, for consistency with Applicant’s disclosure and for the purpose of this Office Action, the Examiner will read the limitation “the second connection pad” of Claim 5 as --a third connection pad--
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (U.S. Pub. 2017/0136582), hereinafter Cheng.
Regarding Claim 1, Cheng teaches an electronic component-incorporating substrate ((100); Fig. 1, Paragraph [0017]), comprising:
-a first substrate ((110); Fig. 1, Paragraph [0017]) including a first connection pad (e.g. rightmost (111); Fig. 1, Paragraph [0018]);
-a second substrate ((120); Fig. 1, Paragraph [0017]) including a second connection pad (e.g. rightmost unmarked pad, hereinafter ‘(P2)’; Fig. 1, Paragraph [0018]) that faces the first connection pad (111);
-a spacer member (rightmost (140); Fig. 1, Paragraph [0017]) electrically connecting the first connection pad and the second connection pad (Paragraph [0019]));
-an electronic component ((130); Fig. 1, Paragraph [0017]) mounted on the first substrate (110) and disposed between the first substrate and the second substrate (120); and
-an encapsulation resin ((150); Fig. 1, Paragraph [0028]) filling a gap between the first substrate (110) and the second substrate (120) and encapsulating the electronic component (130), wherein
-the spacer member (140) includes a spherical solder core ball ((141); Fig. 1, Paragraph [0024]) and a solder layer ((143); Fig. 1, Paragraph [0026]) that covers a circumference (Paragraph [0022]) of the solder core ball (141), and
-a melting point of the solder layer (143) is lower than a melting point of the solder core ball (141) (Paragraph [0023]).
Regarding Claim 5, Cheng teaches an electronic component-incorporating substrate ((100); Fig. 1, Paragraph [0017]), of Claim 1, wherein:
-the electronic component (130) includes a bump (internal core of rightmost (131) that is equivalent to (141); Figs. 1 and 2, Paragraph [0019] and Paragraph [0020]) that electrically connects the electronic component (130) and a third connection pad (e.g. rightmost unmarked pad underneath rightmost (131), hereinafter ‘(P3)’; Fig. 1, Paragraph [0021]), and a melting point of the bump is equal to the melting point of the solder core ball or higher than the melting point of the solder core ball (in this case equal, both being the same material).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (U.S. 2012/0252163), hereinafter Yoo, in view of Sekijima (U.S. Pub. 2022/0399293), hereinafter Sekijima, and Lee et al. (U.S. Pub. 2024/0172371), hereinafter Lee.
Regarding Claim 1, Yoo teaches an electronic component-incorporating substrate ((300); Fig. 4, Paragraph [0044]), comprising:
-a first substrate ((210); Fig. 4, Paragraph [0034]) including a first connection pad (e.g. rightmost (216); Fig. 4, Paragraph [0035]);
-a second substrate ((110); Fig. 4, Paragraph [0027]) including a second connection pad (e.g. rightmost (112); Fig. 4, Paragraph [0028]) that faces the first connection pad (216);
-a spacer member (comprising rightmost (190) and (240)/(240’); Fig. 4, Paragraphs [0032] and [0038]) electrically connecting the first connection pad (112) and the second connection pad (215);
-an electronic component ((230); Fig. 4, Paragraph [0034]) mounted on the first substrate (210) and disposed between the first substrate and the second substrate (110); wherein
-the spacer member includes a spherical solder core ball (190) and a solder layer (240)/(240’) that covers a circumference (See Note Below) of the solder core ball (190).
Examiner’s Note: This limitation is fulfilled in one of two interpretations of the claim limitations:
-“covers” is taken in the broad definition in that the solder is does not completely cover the solder core ball, e.g. (240)/(240’) on the bottom and sides of (190) in Fig. 4
-“a circumference” is taken by referencing a cross section of (190) from a top-down view, i.e. the plane is on the lower portion of the solder core ball (190) such that the solder layer (240)/(240’) completely covers it entirely around.
Yoo does not explicitly disclose:
-an encapsulation resin filling a gap between the first substrate and the second substrate and encapsulating the electronic component,
Sekijima teaches an electronic component-incorporating substrate ((10); Fig. 1, Paragraph [0022]), comprising:
-an encapsulation resin ((40); Fig. 1, Paragraph [0037]) filling a gap between the first substrate ((100); Fig. 1, Paragraph [0022]) and the second substrate ((200); Fig. 1, Paragraph [0022]) and encapsulating the electronic component ((300); Fig. 1, Paragraph [0022])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Sekijima into the device of Yoo such that it comprises an encapsulation resin filling a gap between the first substrate and the second substrate and encapsulating the electronic component. This would be due to the fact that doing so would securely bond the first substrate to the second substrate (Sekijima, Paragraph [0037]).
Neither Yoo nor Sekijima explicitly teach:
-a melting point of the solder layer is lower than a melting point of the solder core ball.
Lee teaches bonding between an upper solder ball ((13)/(130); Figs. 2 and 6, Paragraphs [0040]) and [0075]) and a lower solder layer ((12)/(120); Figs. 2 and 6, Paragraphs [0051]) and [0074]):
-a melting point of the solder layer (139° C; Paragraph [0080]) is lower than a melting point of the solder core ball (‘About 217° C’; Paragraph [0080] – which is recognized as being up to 227° C – See Paragraph [0042], value encompasses 5% deviation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the device of Yoo as modified by Sekijima such that a melting point of the solder layer is lower than a melting point of the solder core ball. This would be due to the fact that doing so would incorporate viable materials to ensure bonding is done at a lower temperature, thereby avoiding component deterioration (Lee, Paragraph [0003]).
Regarding Claim 2, Yoo as modified by Sekijima and Lee teaches an electronic component-incorporating substrate ((300); Fig. 4, Paragraph [0044]), of Claim 1, wherein:
-the melting point of the solder layer (modified Yoo, (240)/(240’)- ‘139° C’; Lee, Paragraph [0080]) is lower than the melting point of the solder core ball (modified Yoo, (190)- ‘227° C’; Lee, Paragraph [0080]) by 20℃ or greater (227 – 139 = 88).
Regarding Claim 3, Yoo as modified by Sekijima and Lee teaches an electronic component-incorporating substrate ((300); Fig. 4, Paragraph [0044]), of Claim 1, wherein:
- the melting point of the solder layer is between 100℃ to 200℃ (modified Yoo, (240)/(240’)- ‘139° C’; Lee, Paragraph [0080]), inclusive, and the melting point of the solder core ball is between 220°C and 280°C (modified Yoo, (190)- ‘227° C’; Lee, Paragraph [0080]), inclusive.
Regarding Claim 4, Yoo as modified by Sekijima and Lee teaches an electronic component-incorporating substrate ((300); Fig. 4, Paragraph [0044]), of Claim 1, wherein:
-a material of the solder layer (modified Yoo, (240)/(240’)) is lead-free solder of a tin-bismuth base or a tin-indium base (Lee, ‘SnBi’; Paragraphs [0004] and [0080]), and a material of the solder core ball (modified Yoo, (190)) is lead-free solder of a tin-silver base or a tin-antimony base (Lee, mixture of Sn, Ag, and Cu known as ‘SAC’; Paragraphs [0003] and [0080]).
Regarding Claim 5, Yoo as modified by Sekijima and Lee teaches an electronic component-incorporating substrate ((300); Fig. 4, Paragraph [0044]), of Claim 1, wherein:
-wherein the electronic component (modified Yoo, (230)) includes a bump (modified Yoo, (225), Paragraph [0036]) that electrically connects the electronic component and a third connection pad (modified Yoo, (225), Paragraph [0036])
Yoo further states:
-the bumps are solder (Paragraph [0036])
Yoo does not explicitly state:
-a melting point of the bump is equal to the melting point of the solder core ball or higher than the melting point of the solder core ball.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Yoo as modified by Sekijima and Lee such that a melting point of the bump is equal to the melting point of the solder core ball or higher than the melting point of the solder core ball. This would be a direct result of using the same soldering material of (modified Yoo, (190)), i.e. the melting point of the bump is equal to the melting point of the solder core ball. This using of the same soldering material would be obvious as doing so would produce the predictable result of incorporating a viable material for solder bonding and consequently simplify manufacturing by using repeated materials.
Prior Art
The prior art below made of record and not relied upon is considered pertinent to applicant's disclosure and may be utilized in alternative rejections under 35 USC § 103:
Mori et al. (U.S. 2012/0319289): Teaches an electronic component-incorporating substrate ((10a); Fig. 4, Paragraph [0028]), comprising first (31) and second (20) substrates (Paragraphs [0022] and [0023]) with first (37) and second (22) connection pads (Paragraphs [0023] and [0026]) connected via a spacer member (e.g. (40); Paragraph [0042]) among other present limitations.
Cho (U.S. 2019/0295997): Teaches an electronic component-incorporating substrate ((10a); Fig. 4, Paragraph [0028]), comprising first (110) and second (210) substrates (Paragraphs [0014] and [0028]) with first (112) and second (214) connection pads (Paragraphs [0015] and [0029]) connected via a spacer member ((38); Paragraph [0029]) among other present limitations.
Kim et al. (U.S. 2021/0320067): Teaches an electronic component-incorporating substrate (Fig. 2, Paragraph [0026]), comprising first (100) and second (200) substrates (Paragraph [0026]) with first (134) and second (14p) connection pads (Paragraphs [0028] and [0046]) connected via a spacer member ((180); Paragraph [0056]) among other present limitations.
Hatori et al. (U.S. 2023/0276575): Teaches an electronic component-incorporating substrate ((1); Fig. 1, Paragraph [0018]), comprising first (30) and second (10) substrates (Paragraph [0018]) with first (34p) and second (14p) connection pads (Paragraphs [0028] and [0035]) connected via a spacer member ((20); Paragraph [0018]) among other present limitations.
Hsu et al. (U.S. 2024/0304450): Teaches an electronic component-incorporating substrate ((3); Fig. 1, Paragraph [0054]), comprising first (1) and second (2) substrates (Paragraph [0054]) with first (141) and second (241) connection pads (Paragraph [0063]) connected via a spacer member ((38); Paragraph [0054]) among other present limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
