DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-41 are pending and examined.
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because the text within the boxes of FIGS. 2 and 6 is blurry and difficult to read. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-41 are rejected under 35 U.S.C. 103 as being unpatentable over US 8,599,600 to Xi et al. (hereafter Xi).
Regarding independent claim 1, Xi teaches a data writing operation method of a resistive random access memory (RRAM), comprising:
applying a first pulse voltage to the resistive random access memory (FIG. 6: forward reset pulse application of VL in step 104; FIG. 7: the first pulse voltage is the first pulse of VL(count)) and adding one to a corresponding first applied pulse number to obtain a FIG. 6: performing step 105 in response to result from step 104);
judging whether the FIG. 6: determining if VL(count)=max in step 106 in response to result from step 104);
judging whether a current second applied pulse number is greater than a second set upper limit value (FIG. 6: determining if VH(count)=max in step 106 in response to result from step 111) if the (it is seen that VL(count) has completed looping and RH has determined greater than LRL before VH(count) is in looping);
testing the resistance state of a resistive random access memory cell to obtain a corresponding test value if the current second applied pulse number is smaller than or equal to the second set upper limit value (FIG. 6: determining if RH < URL in step 109);
judging whether the test value satisfies a preset condition (FIG. 6: either N or Y from step 109); and
if the test value does not satisfy the preset condition, applying a second pulse voltage to the resistive random access memory (FIG. 6: when the result from step 109 is N, looping back to reset pulse application of VH in step 111), and adding one to the corresponding second applied pulse number, to obtain the current second applied pulse number (FIG. 6: performing step 105 in response to result from step 111), until the test value satisfies the preset condition (FIG. 6: until result from RH<URL is a Y in step 109) or the current second applied pulse number is greater than the second set upper limit value (FIG. 6: until result from VH count = max in step 106) to complete a data writing operation of the resistive random access memory, wherein a pulse amplitude greater than those corresponding to the second pulse voltage (see FIGS. 3-4, 6-7).
Xi suggests the forward reset pulse application of VL described in FIGS. 3-4 and 6-7 is seen as set operation, and the reverse reset pulse application of VH as reset operation. However, Xi does not teach:
series of pulses with increasing pulse width and current limiting value (i.e. constant amplitude), but instead a series of VH(count) pulses with decreasing amplitude;
both first and second applied pulse numbers are current applied pulse numbers. Unlike step S2 followed with step S5 in the within same loop as shown in FIG. 6 of pending application, Xi teaches VH(count) is performed after VL(count) has been completed.
Park teaches data writing operation method of a resistive random access memory
(RRAM), comprising a set operation and reset operation. Park further teaches there are more than one approaches for applying pulses during reset operation (see FIGS. 24A-24C), wherein the reset operation comprising applying series of pulses with increasing pulse width and current limiting value (FIG. 24C: i.e. first reset pulse Vreset0 has narrower pulse width than second reset pulse Vreset1, wherein Vreset0 and Vreset1 have constant amplitude).
Since Xi and Park are both from the same field of endeavor, the purpose disclosed by Park would have been recognized in the pertinent art of Xi.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
replace the series of VH(count) pulses in FIG. 7 of Xi with series of Vreset pulses in FIG. 24C of Park in a reset operation of RRAM cells because they appears functional equivalent;
perform applications of VL and VH in different looping as suggested by Xi, or same looping as described in pending application because they appears functional equivalent.
Regarding dependent claim 2, Xi teaches wherein, [during the performance of VL(count)] if the current first applied pulse number is smaller than or equal to the first set upper limit value (FIG. 6: determining if VL(count)=max in step 106 in response to result from step 104), testing the resistance state of the resistive random access memory cell to obtain a corresponding test value, and judging whether the test value satisfies a preset condition (FIG. 6: determining if RH > LRL in step 108), if the test value satisfies the preset condition, completing a data writing operation of the resistive random access memory (i.e. completion VL(count)), and if the test value does not satisfy the preset condition, continuing to apply the first pulse voltage to the resistive random access memory until the test value satisfies the preset condition (i.e. loop back on VL(count)).
Regarding dependent claim 3, Xi teaches wherein, if the current second applied pulse number is greater than the second set upper limit value, completing the data writing operation of the resistive random access memory, and judging that writing is failed (FIG. 6: when result of VH(count)=max in step 106 is Y).
Regarding dependent claim 4, Xi teaches wherein, if the test value satisfies the preset condition, completing the data writing operation of the resistive random access memory is completed, and judging that writing is successful (FIG. 6: when result of step 109 is Y, the process go to reset end).
Regarding dependent claim 5, Xi teaches wherein judging whether the test value satisfies the preset condition comprises: judging whether the test value is greater than or equal to a first set resistance value and smaller than or equal to a second set resistance value, wherein the first set resistance value is smaller than the second set resistance value (FIG. 6: steps 108 and 109).
Regarding dependent claims 6-10, Xi teaches wherein initial values of the first applied pulse number and the second applied pulse number are each set to zero (FIG. 6: the numbers are set to zero in step 101).
Regarding dependent claims 11-20, Xi teaches a computer-readable storage medium having stored thereon a data writing operation program of a resistive random access memory which, when executed by a processor, implements the data writing operation method of the resistive random access memory according to claim 1/2/3/4/5/6/7/8/9/10 (see 4:33-43).
Regarding dependent claims 21-30, Xi teaches a chip, comprising a memory, a processor, and a data writing operation program of a resistive random access memory stored on the memory and operable on the processor, the processor, when executing the data writing operation program of the resistive random access memory, implementing the data writing operation method of the resistive random access memory according to claim 1/2/3/4/5/6/7/8/9/10 (see 4:33-43. There appears the RRAM cells 10 and control unit are in the same memory device).
Regarding dependent claims 31-40, Xi does not explicitly teaches a computer program product comprising a computer program which, when executed by a processor, implements a data writing operation method of a resistive random access memory according to claim 1/2/3/4/5/6/7/8/9/10 (see 4:33-43). However, Xi suggests the implementations of the method is not particularly limited to hardware in order to obtain the method.
Regarding independent claim 41, Xi teaches a data writing operation device of a resistive random access memory, comprising:
a first excitation module, configured to apply a first pulse voltage to the resistive random access memory (FIG. 6: module for forward reset pulse application of VL in step 104; FIG. 7: the first pulse voltage is the first pulse of VL(count)) and add one to a corresponding first applied pulse number to obtain a FIG. 6: performing step 105 in response to result from step 104);
a first judging module, configured to judge whether the FIG. 6: module for determining if VL(count)=max in step 106 in response to result from step 104);
a second judging module, configured to judge whether a current second applied pulse number is greater than a second set upper limit value (FIG. 6: module for determining if VH(count)=max in step 106 in response to result from step 111) if the it is seen that VL(count) has completed looping and RH has determined greater than LRL before VH(count) is in looping);
a test module, configured to test the resistance state of a resistive random access memory cell to obtain a corresponding test value if the current second applied pulse number is smaller than or equal to the second set upper limit value (FIG. 6: module for determining if RH < URL in step 109);
a third judging module, configured to judge whether the test value satisfies a preset condition (FIG. 6: module for determining either N or Y from step 109); and
a second excitation module, configured to, if the test value does not satisfy the preset condition, apply a second pulse voltage to the resistive random access memory (FIG. 6: when the result from step 109 is N, module for looping back to reset pulse application of VH in step 111), and add one to the corresponding second applied pulse number, to obtain the current second applied pulse number (FIG. 6: module for performing step 105 in response to result from step 111), until the test value satisfies the preset condition (FIG. 6: until result from RH<URL is a Y in step 109) or the current second applied pulse number is greater than the second set upper limit value (FIG. 6: until result from VH count = max in step 106) to complete a data writing operation of the resistive random access memory, wherein a pulse amplitude greater than those corresponding to the second pulse voltage (see FIGS. 3-4, 6-7).
Xi suggests the forward reset pulse application of VL described in FIGS. 3-4 and 6-7 is seen as set operation, and the reverse reset pulse application of VH as reset operation. However, Xi does not teach:
series of pulses with increasing pulse width and current limiting value (i.e. constant amplitude), but instead a series of VH(count) pulses with decreasing amplitude;
both first and second applied pulse numbers are current applied pulse numbers. Unlike step S2 followed with step S5 in the within same loop as shown in FIG. 6 of pending application, Xi teaches VH(count) is performed after VL(count) has been completed.
Park teaches data writing operation method of a resistive random access memory
(RRAM), comprising a set operation and reset operation. Park further teaches there are more than one approaches for applying pulses during reset operation (see FIGS. 24A-24C), wherein the reset operation comprising applying series of pulses with increasing pulse width and current limiting value (FIG. 24C: i.e. first reset pulse Vreset0 has narrower pulse width than second reset pulse Vreset1, wherein Vreset0 and Vreset1 have constant amplitude).
Since Xi and Park are both from the same field of endeavor, the purpose disclosed by Park would have been recognized in the pertinent art of Xi.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
replace the series of VH(count) pulses in FIG. 7 of Xi with series of Vreset pulses in FIG. 24C of Park in a reset operation of RRAM cells because they appears functional equivalent;
perform applications of VL and VH in different looping as suggested by Xi, or same looping as described in pending application because they appears functional equivalent.
Conclusion
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June 13, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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