DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 18/928,200 has a total of 24 claims pending in the application; there are 2 independent claim and 22 dependent claims, all of which are ready for examination by the examiner.
IFORMATION CONCENING DRAWING:
3. Application’s drawing submitted on 10/28/2024 are acceptable for examination purposes.
INFORMATION CONCERNING IDS:
4. The information disclosure statement (IDS) submitted on 10/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner.
INFORMATION CONCERNING FOREIGN PRIORITY:
5. Acknowledgment is made of applicant’s claim for foreign priority based on an application filed in Republic of Korea on 05/27/2024.
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claims 12 and 24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
7. Claim 12 recites the limitation(s):
“vary a number of areas to be set as the first selected area among the second physical areas, according to the number of the first compressed data; and vary a number of areas to be set as the second selected area among the second physical areas, according to the number of the second compressed data.
The claimed specification does not appear to describe/support the limitation(s) as claimed. Claim 24 recites similar limitations and rejected based on the same ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over GENG et al. “Geng” (US 2023/0236979 A1) in view of KORNIENKO et al. “Kornienko” (US 2021/0133922 A1).
8. Regarding claim 1, Geng teaches or suggests:
“A storage device (e.g., Fig. 1) comprising: a volatile memory (e.g., Fig. 1, ¶ 0062, system DRAM 112) comprising a plurality of physical areas;” (e.g., ¶ 0020, a plurality of data regions; Fig. 2A, ¶ 0063, a plurality of memory blocks (e.g., blocks 202-206, blocks 216-222); Fig. 2A, ¶ 0065, a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address).
“and a control operation circuit configured to divide the plurality of physical areas included in the volatile memory into first physical areas and second physical areas,” (e.g., ¶ 0020, The compressed memory system includes a memory partitioning circuit configured to partition a memory region into a plurality of data regions; Fig. 2A, ¶ 0063, Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206); Fig. 2A, ¶ 0065, a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address; Fig. 2A, ¶ 0071, the compressed memory system 200 includes a register file 208 that holds base pointers for the blocks 202, 204, and 206, and the metadata circuit 210 provides offsets from the base pointers for the blocks). Geng teaches that compressed memory system 200 in Fig. 2A (e.g., DRAM 112 shown in Fig. 2A Comprises: regions (e.g., areas) partitioned (e.g., divided) to store compressed data (e.g., regions 202 -206), free blocks 216 – 222, meta data 210, and registers 208 (e.g., a register file). The combination of a base address (e.g., pointers) and the corresponding offset (e.g., metadata entries) provides an address to identify a memory location storing compressed data (e.g., mapping virtual address to physical address).
“store the first compressed data in the first physical areas,” (e.g., Fig. 2A, ¶ 0063, Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206)… as shown in FIG. 1, the compress circuit may be configured to compress 64-byte (64B) data words down to 48-byte (48B) compressed data words, 32-byte (32B) compressed data words, or 16-byte (16B) compressed data words, which can be stored in respective memory blocks 202(64B), 204(48B), 206(32B), and 204(48B), 206(32B), and 204(16B) 20and 204(16B). Geng teaches that a 64-byte data word (e.g., 64B) is compressed to smaller sizes and are written to a plurality of memory blocks. For example, Fig. 2A shows a 48B compressed data is written to memory blocks 204 (e.g., the first physical area). It should be noted that each entry or line of memory is 64-byte word wide. It may possible to store more than one compressed data per entry as shown by vertical lines in blocks 204 and 206 in Fig. 2A.
“and store first logical information indicating an area storing the first compressed data, in a first selected area of the second physical areas.” (e.g., Fig. 2A, ¶ 0071, the compressed memory system 200 includes a register file 208 that holds base pointers for the blocks 202, 204, and 206, and the metadata circuit 210 provides offsets from the base pointers for the blocks; Fig. 2A, ¶ 0065, the compression circuit provides the virtual address for the memory read request to a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address of the memory read request). Geng teaches that combination of a base pointer and offset generate an address that is used to access compressed data stored in the memory. Geng does not expressly recites storing logical information but teaches that metadata circuit 210 stores virtual information (e.g., offsets) that indicates the block entry or location in which the compressed data is stored. The metadata information comprising virtual offsets comprises/represents logical information recited in claim. Geng teaches the write data (e.g., 64-byte (64B) data words) compressed to generated compressed data of reduced sizes 48B, 32B, and 16B (e.g., Fig. 2A and ¶ 0065 of Geng). However, Geng does not expressly teach while:
Kornienko discloses: “a compression operation circuit configured to compress write data at a first rate to generate first compressed data;” (e.g., ¶ 0032, A plurality of different compression rates may be used to compress the input data; claim 2, wherein a first compression module is arranged to produce compressed input data at a first compression rate) for compressing input data (e.g., write data) at a first compression rate to produce (e.g., generate) first compressed data.
Disclosures by Geng and Kornienko are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the priority-based cache-line fitting in compressed memory systems of processor-based systems taught by Geng to include the compression rate for compressing input data disclosed by Kornienko.
The motivation for including the compression rate for compressing input data includes increasing system efficiency (e.g., see paragraphs [0029] of Kornienko).
Therefore, it would have been obvious to combine teaching of Kornienko with Geng to obtain the invention as specified in the claim.
9. Regarding claim 13, Geng teaches or suggests:
“An operating method of a storage device including a volatile memory (Fig. 2C, ¶ 0073, a method for writing cache lines using the compressed memory system shown in FIG. 2A) , the operating method comprising: dividing a plurality of physical areas included in the volatile memory into first physical areas and second physical areas;” (e.g., ¶ 0020, The compressed memory system includes a memory partitioning circuit configured to partition a memory region into a plurality of data regions; Fig. 2A, ¶ 0063, Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206); Fig. 2A, ¶ 0065, a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address; Fig. 2A, ¶ 0071, the compressed memory system 200 includes a register file 208 that holds base pointers for the blocks 202, 204, and 206, and the metadata circuit 210 provides offsets from the base pointers for the blocks). Geng teaches that compressed memory system 200 in Fig. 2A (e.g., DRAM 112 shown in Fig. Comprises: regions (e.g., areas) partitioned (e.g., divided) to store compressed data (e.g., regions 202 -206), free blocks 216 – 222, meta data 210, and registers 208 (e.g., a register file). The combination of a base pointer and the corresponding offset provides an address to identify a memory location storing compressed data (e.g., mapping virtual address to physical address).
“storing the first compressed data in the first physical areas;” (e.g., Fig. 2A, ¶ 0063, Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206)… as shown in FIG. 1, the compress circuit may be configured to compress 64-byte (64B) data words down to 48-byte (48B) compressed data words, 32-byte (32B) compressed data words, or 16-byte (16B) compressed data words, which can be stored in respective memory blocks 202(64B), 204(48B), 206(32B), AND 204(48B), 206(32B), and 204(16B) 20and 204(16B). Geng teaches that a 64-byte data word (e.g., 64B) is compressed to smaller sizes and are written to a plurality of memory blocks. For example, Fig. 2A shows a 48B compressed data is written to memory blocks 204 (e.g., the first physical area). It should be noted that each entry or line of memory is 64-byte word wide. It may possible to store more than one compressed data pe entry as shown by vertical lines in blocks 204 and 206 in Fig. 2A.
“and storing first logical information indicating an area storing the first compressed data in a first selected area of the second physical areas.” (e.g., Fig. 2A, ¶ 0071, the compressed memory system 200 includes a register file 208 that holds base pointers for the blocks 202, 204, and 206, and the metadata circuit 210 provides offsets from the base pointers for the blocks; Fig. 2A, ¶ 0065, the compression circuit provides the virtual address for the memory read request to a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address of the memory read request). Geng teaches that combination of a base pointer (e.g., address) and offset generate an address that is used to access compressed data stored in the memory. Geng does not expressly recites storing logical information but teaches that metadata circuit 210 stores virtual information (e.g., offsets) that indicates the block entry or location in which the compressed data is stored. The metadata information comprising virtual offsets comprises/represents logical information recited in claim. Geng teaches the write data (e.g., 64-byte (64B) data words) compressed to generated compressed data of reduced sizes 48B, 32B, and 16B (e.g., Fig. 2A and ¶ 0065 of Geng). The metadata offsets stored in metadata circuit 210 comprises logical information. A metadata offset in combination with a corresponding base pointer stored in the registers 208 provide an address a location storing compressed data (e.g., 48B in blocks 204, Fig. 2A). However, Geng does not expressly teach while:
Kornienko discloses: ““compressing write data at a first rate to generate first compressed data” (e.g., ¶ 0032, A plurality of different compression rates may be used to compress the input data; claim 2, wherein a first compression module is arranged to produce compressed input data at a first compression rate) for compressing input data (e.g., write data) at a first compression rate to produce (e.g., generate) first compressed data. The motivation for combining is based on the same rational presented for rejection of independent claim 1.
10. Regarding claims 2 and 14, Geng further teaches:
“wherein the compression operation circuit is configured to compress the write data (e.g., Fig. 2A, ¶ 0063, the compress circuit may be configured to compress 64-byte (64B) data words down to 48-byte (48B) , 206(32B) compressed data words, and wherein the control operation circuit is configured to: store the second compressed data in the first physical areas;” (Fig. 2A, ¶ 0063, compressed data words, which can be stored in respective memory blocks 202(64B), 204(48B), 206(32B)). The 64B size is the same size as input write data (e.g., with no or zero compression). The Examiner has chosen the 48B as the first compressed data and 32B as the second compressed data recited in claims.
“and store second logical information indicating an area storing the second compressed data, in a second selected area of the second physical areas.” (e.g., Fig. 2A, ¶ 0071, the compressed memory system 200 includes a register file 208 that holds base pointers for the blocks 202, 204, and 206, and the metadata circuit 210 provides offsets from the base pointers for the blocks; Fig. 2A, ¶ 0065, the compression circuit provides the virtual address for the memory read request to a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address of the memory read request). The metadata offsets stored in metadata circuit 210 comprises logical information. A metadata offset in combination with a corresponding base pointer stored in the registers 208 provide an address a location storing compressed data (e.g., 32B in blocks 206, Fig. 2A).
Kornienko discloses: “compress the write data at a second rate” (e.g., ¶ 0032, A plurality of different compression rates may be used to compress the input to data; claim 2, wherein a second compression module is arranged to produce compressed input data at a second compression rate).
11. Regarding claims 3 and 15, Geng further teaches:
“set some of a current number of free areas as management areas to store free area information on the free areas that are available for storing data, among the first physical areas; and manage the management areas in a form of a linked list.” (e.g., Fig. 2A, ¶ 0068, entry to one of free memory lists (e.g., list of free 64B blocks 216, list of free 48B blocks 218, list of free 32B blocks 220, and list of free 16B blocks 222) of pointers to available memory blocks in the compressed data region. The compress circuit then obtains the pointer from one of the free memory lists to the new, available memory block of desired memory block size in the compressed data region to store the compressed data region).
Claims 4, 6, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Geng in view of Kornienko as applied to claims 4 and 15 above, and further in view of Oikawa “Oikawa” (US 2012/0131264 A1).
12. Regarding claims 4 and 16, Geng in view of Kornienko teach all limitations included in claim 3 and 15 but do not appear to expressly teach while Oikawa discloses:
“select a first storage area from the free areas with reference to the free area information;” (Fig. 3, ¶ 0035, The free page list 24 has entries, each consisting of a physical page address. The free page list 24 holds the physical addresses of the first data pages of the free areas provided in the block as the data compressed in units of blocks is stored in the block; Fig. 4, ¶ 0040, As shown in FIG. 4, an area to which data can be written in units of blocks is acquired from the free block list 25 in Step S1)
““store the first compressed data in the selected first storage area;” (e.g., Fig. 4, ¶ 0044, in Step S6, the data block compressed is written. More precisely, the data block compressed in Step S5 is written to the storage memory 11).
generate the first logical information indicating the first storage area;” (e.g., Fig. 4, ¶ 0044, in Step S6, the data block compressed is written. More precisely, the data block compressed in Step S5 is written to the storage memory 11).
“store the first logical information in the first selected area;” (e.g., Fig. 4, ¶ 0045, in Step S4, the physical address to which the compressed data block is written is set in the block conversion table 23).
“and invalidate, from the management area, information corresponding to the first storage area, among the free area information.” ;” (Fig. 3, ¶ 0037, not only the free block list 25 can manage any block in which all data is invalidated, but also the free page list 24 can manage, as a data page, that part (free area) of any block, which has been made free (invalidated) because the data block is compressed) for setting a block or any portions of that are invalidated as free.
Disclosures by Geng, Kornienko, and Oikawa are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the priority-based cache-line fitting in compressed memory systems of processor-based systems taught by Geng to include the compression rate for compressing input data disclosed by Kornienko; Furthermore, to include storing compressed data according to information free list information taught by Oikawa.
The motivation for including the compression rate for compressing input data includes increasing system efficiency (e.g., see paragraphs [0029] of Kornienko); furthermore, the motivation for writing compressed data as taught by paragraph [0075] of Oikawa includes reducing an increase in processing time.
Therefore, it would have been obvious to combine teachings of Oikawa and Kornienko with Geng to obtain the invention as specified in the claim.
13. Regarding claims 6 and 18, Oikawa further teaches:
“select a second storage area from the free areas with reference to the free area information;” (e.g., Fig. 4, ¶ 0044, an area to which data can be written in units of blocks is acquired from the free block list 25 in Step S1; Figs. 2-3, ¶ 0037, not only the free block list 25 can manage any block in which all data is invalidated, but also the free page list 24 can manage, as a data page, that part (free area) of any block, which has been made free (invalidated) because the data block is compressed).
“store the second compressed data in the selected second storage area;” (e.g., Fig. 4, ¶ 0044, in Step S6, the data block compressed is written. More precisely, the data block compressed in Step S5 is written to the storage memory 11).
“generate the second logical information indicating the second storage area;” (e.g., Fig. 2, ¶ 0030, As shown in FIG. 2, the work memory 12 is composed of a data buffer 21, a page conversion table 22, a block conversion table 23, a free page list 24; Fig. 6, ¶ 0071, the free area (e.g., part of the upper page) generated by writing the compressed data block). The free are maintained in the free page list 24 and free block list 25 (Figs. 2-3). Invalidating data generates free storage area
“store the second logical information in the second selected area;” (e.g., Fig. 2-3, ¶ 0036, The free block list 25 holds the physical addresses of blocks in which all data is invalidated).
“and invalidate, from the management area, information corresponding to the second storage area, among the free area information.” (claim 6, the free block list holds physical address of each of blocks in which all data is invalidated).
Allowable Subject Matter
14. Claims 5, 7-11, 17, and 19-23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
the prior art made of record and not relied upon are as follows:
1. Zhao et al. (US 20220100707 A1) teaches “… compressing a first data block by a first compression rate to obtain a first compressed data, and compressing the first data block by a second compression rate to obtain a second compressed data…” (par. [0048]).
2. Yeh (US 20160110112 A1) teaches “… the memory management circuit, wherein the memory management circuit identifies whether data belongs to a first pattern or a second pattern, if the data belongs to the first pattern, the first compression/decompression circuit compresses the data to generate compressed data, and the memory management circuit issues a command sequence to write the compress data into the physical programming units, and if the data belongs to the second pattern, the second compression/decompression circuit compresses the data to generate another compressed data, and the memory management circuit issues a command sequence to write the another compressed data into the physical programming units…” (claim 7).
3. Abdo et al. (US 20080005801 A1) teaches “…compressing data in variable rate…” (par. 27)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/ Primary Examiner, Art Unit 2138