Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8, 11-16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida et al. (US Pub # 2008/0088264).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Tsuchida et al. teach a voltage converter comprising: a voltage converting circuit configured to convert an input voltage into an output voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052 where unit 12/21 voltage converter, output voltage Vo); an offset generation circuit configured to generate an offset voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit 22 offset generation ckt); a ripple addition circuit configured to receive the output voltage and a first voltage from the voltage converting circuit, to receive the offset voltage from the offset generation circuit, and to generate a ripple voltage based on the output voltage, the first voltage, and the offset voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit 23 receive output voltage Vo, first voltage and offset voltage from unit 23, Ripple voltage Vo1); and a controller configured to receive the ripple voltage, to control switches in the voltage converting circuit based on the ripple voltage, and to control a timing at which the offset generation circuit generates the offset voltage and a timing at which the offset generation circuit does not generate the offset voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit (4 +10) is controller, receive ripple voltage Vo1, unit 10 generate output signal to control offset circuit 22 and unit 4 generate voltage VN to control voltage converter).
Even though Tsuchida et al. teach output voltage from the adder circuits 23 but silent exclusively about ripple voltage. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Tsuchida et al. where voltage Vo1 is generated based on output voltage Vo and offset voltage from 22 and offset voltage varies based on target voltage (see specially paragraph 0038) to generate ripple output voltage and would be called ripple voltage in order to have controlled output voltage and current for the converter circuits.
Regarding claim 2, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Tsuchida et al. further teach, wherein the controller is configured to cause the offset generation circuit to generate the offset voltage during a time period when the output voltage rises, and to prevent the offset generation circuit from generating the offset voltage during a time period when the output voltage falls (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049).
Regarding claim 3, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Tsuchida et al. further teach, wherein the controller includes a comparator configured to compare the ripple voltage with a reference voltage and to generate a comparator voltage as a result of the comparison, and wherein the offset voltage is determined based on a hysteresis of the comparator (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051).
Regarding claim 4, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Tsuchida et al. further teach, wherein a level of the offset voltage is determined to be equal to or greater than a level of the hysteresis of the comparator (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0047).
Regarding claim 8, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Tsuchida et al. further teach, wherein the ripple addition circuit is configured to generate a ripple based on the first voltage, and to add the ripple and the offset voltage to the output voltage so as to be output as the ripple voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0048).
Regarding claim 11, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Tsuchida et al. further teach, wherein the voltage converting circuit includes: a first switch electrically connecting an output node where the output voltage is output to an input node where the input voltage is received; and a second switch electrically connecting the output node to a ground node to which a ground voltage is supplied (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049).
Regarding claim 12, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Tsuchida et al. further teach, wherein the controller includes: a comparator configured to compare the ripple voltage with a reference voltage and to output a comparison voltage as a result of the comparison; and a timing controller configured to generate a first control signal to turn on and turn off the first switch, and to generate a second control signal to turn on and turn off the second switch, based on the comparison voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051).
Regarding claim 13, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 12 on which this claim depends.
Tsuchida et al. further teach, wherein the controller allows the offset generation circuit to generate the offset voltage using the first control signal (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046).
Regarding claim 14, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Tsuchida et al. further teach, wherein the controller has a first operating mode for controlling the first switch and the second switch in a first manner and a second operating mode for controlling the first switch and the second switch in a second manner, and wherein, in the first operating mode, the controller is configured to control the timing at which the offset generation circuit generates the offset voltage and the timing at which the offset generation circuit does not generate the offset voltage, and wherein, in the second operating mode, the controller allows the offset generation circuit not to generate the offset voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052).
Regarding claim 15, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Tsuchida et al. further teach, wherein, in the first operating mode, the controlleris configured to repeat turning on the first switch during a first time period and turning off the second switch, and turning off the first switch during a second time period and turning on the second switch (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0047).
Regarding claim 16, Tsuchida et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Tsuchida et al. further teach, wherein, in the second operating mode, the controlleris configured to repeat turning on the first switch during a first time period and turning off the second switch, turning off the first switch during a second time period and turning on the second switch, and turning off the first switch during a third time period and turning off the second switch (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051).
Regarding independent claim 20, Tsuchida et al. teach a method of operating a voltage converter, the method comprising: based on a switching control signal, converting an input voltage to generate an output voltage from the input voltage voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052 where unit 12/21 voltage converter, output voltage Vo); in a first time period, generating a ripple voltage by adding a ripple and an offset to the output voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit 22 offset generation ckt); in a second time period, generating the ripple voltage by adding the ripple to the output voltage; and adjusting a timing of converting the input voltage based on the ripple voltage in the first time period and the second time period (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit 23 receive output voltage Vo, and offset voltage from unit 23, Ripple voltage Vo1).
Even though Tsuchida et al. teach output voltage from the adder circuits 23 but silent exclusively about ripple voltage. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Tsuchida et al. where voltage Vo1 is generated based on output voltage Vo and offset voltage from 22 and offset voltage varies based on target voltage (see specially paragraph 0038) to generate ripple output voltage and would be called ripple voltage in order to have controlled output voltage and current for the converter circuits.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida et al. (US Pub # 2008/0088264) in view of Piccardi (US Pub # 2022/0172789).
Regarding independent claim 17, Tsuchida et al. teach a memory module comprising: a plurality of memory devices; a driver configured to receive commands, addresses, and clock signals from an external device, and to transfer the commands, the addresses, and the clock signals to the plurality of memory devices; and a voltage converter configured to receive an input voltage from the external device, to convert the input voltage into an output voltage voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052 where unit 12/21 voltage converter, output voltage Vo), and to provide the output voltage to the plurality of memory devices, wherein the voltage converter includes: a voltage converting circuit configured to convert the input voltage into the output voltage; an offset generation circuit configured to generate an offset voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit 22 offset generation ckt); a ripple addition circuit configured to receive the output voltage and a first voltage from the voltage converting circuit, to receive the offset voltage from the offset generation circuit, and to generate a ripple voltage based on the output voltage, the first voltage, and the offset voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit 23 receive output voltage Vo, first voltage and offset voltage from unit 23, Ripple voltage Vo1); and a controller configured to receive the ripple voltage, to control the voltage converting circuit based on the ripple voltage, and to control a timing at which the offset generation circuit generates the offset voltage and a timing at which the offset generation circuit does not generate the offset voltage (see Fig.1, 3, 4-6 and paragraph 0007-0022, 0033, 0037-0044, 0046-0049, 0051-0052, unit (4 +10) is controller, receive ripple voltage Vo1, unit 10 generate output signal to control offset circuit 22 and unit 4 generate voltage VN to control voltage converter).
Even though Tsuchida et al. teach output voltage from the adder circuits 23 but silent exclusively about ripple voltage. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Tsuchida et al. where voltage Vo1 is generated based on output voltage Vo and offset voltage from 22 and offset voltage varies based on target voltage (see specially paragraph 0038) to generate ripple output voltage and would be called ripple voltage in order to have controlled output voltage and current for the converter circuits.
Allowable Subject Matter
Claims 5-7, 9-10 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: wherein the offset generation circuit includes: a first transistor including a first terminal connected to a power node to which a power supply voltage is supplied, a second terminal configured to output the offset voltage, and a gate connected to a first node; a second transistor including a third terminal connected to the power node, a fourth terminal connected to the first node, and a second gate connected to the first node; a variable resistor connected between the first node and a second node; and a third transistor including a fifth terminal connected to the second node, a sixth terminal connected to a ground node to which a ground voltage is supplied, and a third gate configured to receive a control signal from the controller.
Claim 9 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: wherein the ripple addition circuit includes: a voltage divider configured to receive the first voltage, and to divide the first voltage so as to be output; a noise suppression circuit configured to suppress noise of the output voltage so as to be transmitted to an offset node; a first filter configured to perform low-pass filtering on the divided first voltage so as to be transferred to the offset node; and a second filter configured to perform high-pass filtering on a voltage of the offset node so as to be output as the ripple voltage.
Claim 18 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
wherein the offset generation circuit includes: a first transistor including a first terminal connected to a power node to which a power supply voltage is supplied, a second terminal configured to output the offset voltage, and a gate connected to a first node; a second transistor including a third terminal connected to the power node, a fourth terminal connected to the first node, and a second gate connected to the first node; a variable resistor connected between the first node and a second node; and a third transistor including a fifth terminal connected to the second node, a sixth terminal connected to a ground node to which a ground voltage is supplied, and a third gate configured to receive a control signal from the controller.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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