DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 April 2026 has been entered. Claims 1-20 are pending.
Response to Arguments
Applicant's arguments filed 16 April 2026 have been fully considered but they are not persuasive.
Regarding Claims 11 and 20. Applicant states that the deficiencies noted in Claims 11 and 20 have been corrected by amendment.
The Examiner respectfully disagrees with Applicant’s statement. The claims filed 16 April 2026 contain the original version of Claims 11 and 20.
Regarding Claim 1. The Applicant argues Feng (US 2024/0306442) fails to teach a plurality of sub-bias scan lines spaced apart from each other in the first direction and a connecting line connected to the sub-bias scan lines, wherein in a layer where the sub-bias scan lines are arranged, conductors are not disposed between the sub-bias scan lines in the first direction, as required by Claim 1.
The Examiner respectfully disagrees with Applicant. The Examiner notes the arguments filed 16 April 2026 refer to the connection line as conductor 83 while the Office Action filed 18 February 2026 refers to the connection line as fig. 11b @92.
Feng teaches: a plurality of sub-bias scan lines (fig. 9b @42 illustrates two sub-bias scan lines, discontinuous in the first (x) direction) spaced apart from each other in the first direction and a connecting line (fig. 11b @92) connected to the sub-bias scan lines (¶0104, “In another exemplary implementation mode, a second scan signal line 42 in at least one sub-pixel is provided with a second fracture K2 that cuts off the second scan signal line 42, and second scan signal lines 42 on both sides of the second fracture K2 are connected through a second signal connection electrode 92”), wherein
in a layer where the sub-bias scan lines are arranged, conductors are not disposed between the sub-bias scan lines in the first direction [0037] teaches fig. 9a illustrates the second conductive layer and [0039] illustrates the third conductive layer. Fig. 9a illustrates in the second conductive layer, conductors are not disposed between 42 in the X direction.
Claim Objections
Claims 11 and 20 are objected to because of the following informalities: The limitation “among the transistors” and “each of the transistors” should read “among the plurality of transistors” and “each of the plurality of transistors” to provide proper antecedent basis with “a plurality of transistors”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7, 11-12, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang (US 2025/0232722) in view of Feng (US 2024/0306442). All reference is to Jiang unless otherwise indicated.
Regarding Claim 1 (Currently Amended), Jiang teaches a display device comprising:
a scan line [construed as control signal lines (fig. 4 @81-85)] extending in a first direction [fig. 4 @Horizontal], wherein the scan line [fig. 4 @81-83] includes
a write [¶0080, “a data writing transistor T4”] scan line [fig. 4 @81],
a compensation [¶0080, “a compensation transistor T2”] scan line [fig. 4 @82] and a bias [¶0099, “node N3 are reset to a high voltage by the third reset transistor T8, which is equivalent to adding a negative bias voltage”] scan line [fig. 4 @84];
a data [fig. 2 @Data] line [fig. 14 @91] extending in a second direction [fig. 14 @vertical] crossing the first direction [fig. 4 @Horizontal]; and
a pixel connected to the scan line and the data line [¶0037, “FIG. 2 shows an equivalent circuit diagram of a pixel driving circuit of a display substrate”], wherein
a bias voltage [¶0099, ““the node N3 are reset to a high voltage by the third reset transistor T8, which is equivalent to adding a negative bias voltage to the gate-source electrode of the driving transistor T3”] is applied to the pixel in response to a bias scan signal applied thereto through the bias scan line [fig. 4 @84]
Jiang does not teach the bias scan line includes a plurality of sub-bias scan lines spaced apart from each other in the first direction; and a connecting line connected to the sub-bias scan lines, and wherein in a layer where the sub-bias scan lines are arranged, conductors are not disposed between the sub-bias scan lines in the first direction
Feng teaches a bias scan line [fig. 5 @42] includes
a plurality of sub-bias scan lines [fig. 9b @portion of 42 left of K2 and portion of 42 right of K2] spaced apart from each other in the first direction [fig. 9b @X];
and a connecting line [fig. 11b @92] connected to the sub-bias scan lines [fig. 9b @portion of 42 left of K2 and portion of 42 right of K2], and wherein
in a layer [¶0037, “FIG. 9a and Fig. 9b are schematic diagrams after a pattern of a second conductive layer”] where the sub-bias scan lines [fig. 9b @42] are arranged, conductors are not disposed between the sub-bias scan lines in the first direction [fig. 9b @X, fig. 9b illustrates the claimed structure]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of providing display scan signal lines comprising unequal widths and through holes, as taught by Feng, into the display device taught by Jiang, in order to reduce parasitic capacitances between the second scan signal line 42, and the first power supply line, the data signal line, and the compensation signal line (Feng: ¶0158).
Regarding Claim 2 (Original), Jiang in view of Feng teaches the display device of Claim 1, wherein
the connecting line [Feng: fig. 11b @92] is disposed in a layer different [Feng: fig. 9b is 2nd conductive layer and 11b is 3rd conductive layer] from a layer in which the sub-bias scan lines [feng: fig. 9b @portion of 42 left of K2 and portion of 42 right of K2] are disposed.
Regarding Claim 3 (Original), Jiang in view of Feng teaches the display device of Claim 2, wherein
the connecting line [Feng: fig. 11b @92 ] is disposed above [Feng: fig. 9b is 2nd conductive layer and 11b is 3rd conductive layer] the sub-bias scan lines [Feng: fig. 9b @portion of 42 left of K2 and portion of 42 right of K2].
Regarding Claim 4 (Original), Jiang in view of Feng teaches the display device of Claim 1, wherein the pixel [fig. 1 @PX] includes:
a first pixel circuit [fig. fig. 1 @SP1],
a second pixel circuit [fig. 1 @SP2], and
a third pixel circuit [fig. 1 @SP3], which are arranged in the first direction [fig. 1 @Horizontal]; and
light emitting elements [fig. 4 @OLED, ¶0072] connected to the first, second, and third pixel circuits [fig. 5 @P1-P3], respectively [¶0005, “a plurality of pixel driving circuits provided on the base substrate, the plurality of pixel driving circuits are arranged in the first direction and the second direction, the plurality of pixel driving circuits are configured to drive the light emitting elements of the plurality of sub-pixels respectively”, ¶0037, “FIG. 2 shows an equivalent circuit diagram of a pixel driving circuit”].
Regarding Claim 7 (Original), Jiang in view of Feng teaches the display device of Claim 1, wherein
the data line is provided in plural [Feng: fig. 5 @70],
the pixel is provided in plural [Feng: fig. 5 @P1-P4],
the connecting line is provided in plural [Feng: fig. 5 illustrates single connector 92 that fig 2 teaches repeats a plurality of times], and
the sub-bias scan lines include three or more sub-bias scan lines [Feng: fig. 5 illustrates two sub scan lines 42 that fig 2 teaches repeats a plurality of times], and wherein
a plurality of pixels [Feng: fig. 5 @P1-P4], a plurality of connecting lines [Feng: fig. 5 @92], and the three or more sub-bias scan lines [Feng: fig. 5 @42 left of 92] are arranged in the first direction [Feng: fig. 5 @X].
Regarding Claim 11 (Original), Jiang in view of Feng teaches the display device of Claim 1, wherein the pixel includes:
a plurality of transistors [Feng: fig. 4 @T1-T3] connected to the data line [Feng: fig. 4 @D], the write scan line [Feng: fig. 4 @S1], and the bias scan line [fig. 2 @PReset]; and
a light emitting element [fig. 2 @130] connected to a corresponding transistor [fig. 2 @T4 via T3 and T6] among the transistors, wherein
each of the transistors [fig. 2 @T4 and T8] includes: a semiconductor layer [fig. 6 @T4 and T8] including a source area, a channel area, and a drain area [fig. 50 illustrates claimed structure for T2 which is construed as representative of T4 and T8]; and
a gate electrode [fig. 50 @822] disposed over the semiconductor layer [fig. 50 @22], and wherein
the sub-bias scan lines [Feng: fig. 9b @42] are disposed in a same layer [Feng: fig. 9b illustrates the second conductive layer] as the gate electrode.
Regarding Claim 12 (Original), Jiang in view of Feng teaches the display device of Claim 11, wherein
the connecting line [Feng: fig. 11b @92] is disposed above [Feng: fig. 11b is 3rd conductive layer, fig. 9b is 2nd conductive layer] the gate electrode [Feng: fig. 9b @41-1].
Regarding Claim 18 (Currently Amended), Jiang teaches a display device comprising:
a scan line [construed as control signal lines (fig. 4 @81-85)] extending in a first direction [fig. 4 @Horizontal], wherein the scan line [fig. 4 @81-83] includes
a write [¶0080, “a data writing transistor T4”] scan line [fig. 4 @81],
a compensation [¶0080, “a compensation transistor T2”] scan line [fig. 4 @82] and a bias [¶0099, “node N3 are reset to a high voltage by the third reset transistor T8, which is equivalent to adding a negative bias voltage”] scan line [fig. 4 @84];
a plurality of data lines [fig. 14 @91, ¶0080, “a data line 91 (corresponding to a data signal Data in FIG. 2)”], extending in a second direction [fig. 14 @vertical] crossing the first direction [fig. 4 @Horizontal]; and
a plurality of pixels [¶0005, “a plurality of sub-pixels provided on the base substrate … the plurality of sub-pixels are arranged in a first direction”] arranged in the first direction and connected to the scan line and the data lines [¶0037, “FIG. 2 shows an equivalent circuit diagram of a pixel driving circuit of a display substrate”],
wherein a bias voltage [¶0099, ““the node N3 are reset to a high voltage by the third reset transistor T8, which is equivalent to adding a negative bias voltage to the gate-source electrode of the driving transistor T3”], is applied to the pixel in response to a bias scan signal applied thereto through the bias scan line [fig. 4 @84]
Jiang does not teach the bias scan line includes a plurality of sub-bias scan lines spaced apart from each other in the first direction; and a connecting line connected to the sub-bias scan lines, and wherein in a layer where the sub-bias scan lines are arranged, conductors are not disposed between the sub-bias scan lines in the first direction
Feng teaches a bias scan line [fig. 5 @42] includes:
a plurality of sub-bias scan lines [fig. 9b @portion of 42 left of K2 and portion of 42 right of K2] spaced apart from each other [construed as first sub-bias scan line is separated from the next first sub-bias scan line] for at least one pixel [fig. 5 illustrates first sub-bias scan line (fig. 5 left of K2) spaced by P3 and P4 (two pixels) from the next first sub-bias scan line]; and
a plurality [fig. 5 @P1-P5 repeats as illustrated in fig. 2] of connecting lines [fig. 11b @92] connected to the sub-bias scan lines and wherein
in a layer [¶0037, “FIG. 9a and Fig. 9b are schematic diagrams after a pattern of a second conductive layer”] where the sub-bias scan lines [fig. 9b @42] are arranged, conductors are not disposed between the sub-bias scan lines in the first direction [fig. 9b @X, fig. 9b illustrates the claimed structure]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of providing display scan signal lines comprising unequal widths and through holes, as taught by Feng, into the display device taught by Jiang, in order to reduce parasitic capacitances between the second scan signal line 42, and the first power supply line, the data signal line, and the compensation signal line (Feng: ¶0158).
Regarding Claim 19 (Original), Jiang in view of Feng teaches the display device of Claim 18, wherein
the connecting lines [Feng: fig. 11b @92] are disposed above [Feng: fig. 9b is 2nd conductive layer and 11b is 3rd conductive layer] the sub-bias scan lines [Feng: fig. 9b @portion of 42 left of K2 and portion of 42 right of K2] and connected to the sub-bias scan lines [Feng: abstract].
Regarding Claim 20 (Currently Amended), Jiang teaches an electronic device comprising:
a scan line [construed as control signal lines (fig. 4 @81-85)] extending in a first direction [fig. 4 @Horizontal], wherein
the scan line [fig. 4 @81-83] includes
a write [¶0080, “a data writing transistor T4”] scan line [fig. 4 @81],
a compensation [¶0080, “a compensation transistor T2”] scan line [fig. 4 @82]
and a bias [¶0099, “node N3 are reset to a high voltage by the third reset transistor T8, which is equivalent to adding a negative bias voltage”] scan line [fig. 4 @84];
a data [fig. 2 @Data] line [fig. 14 @91] extending in a second direction [fig. 14 @vertical] crossing the first direction [fig. 4 @Horizontal]; and
a pixel connected to the scan line and the data line [¶0037, “FIG. 2 shows an equivalent circuit diagram of a pixel driving circuit of a display substrate”], wherein
a bias voltage [¶0099, ““the node N3 are reset to a high voltage by the third reset transistor T8, which is equivalent to adding a negative bias voltage to the gate-source electrode of the driving transistor T3”] is applied to the pixel in response to a bias scan signal applied thereto through the bias scan line [fig. 4 @84]; and
the pixel includes: a plurality of transistors [fig. 2 @T8 and T3] connected to the bias scan line [fig. 2 @Preset]
Jiang does not teach two sub-bias scan lines spaced apart from each other in the first direction; and a connecting line connected to the two sub-bias scan lines, wherein the pixel includes: a plurality of transistors connected to the data line, the write scan line; and a light emitting element connected to a corresponding transistor among the transistors, and wherein the two sub-bias scan lines are disposed in a same layer as gate electrodes of the transistors, and the connecting line is disposed above the gate electrodes, and wherein in a layer where the sub-bias scan lines are arranged, conductors are not disposed between the sub-bias scan lines in the first direction
Feng teaches two sub-bias scan lines [fig. 9b @portion of 42 left of K2 and portion of 42 right of K2] spaced apart from each other in the first direction [fig. 9b @Horizontal]; and
a connecting line [fig. 11b @92] connected to the two sub-bias scan lines [fig. 9b @portion of 42 left of K2 and portion of 42 right of K2], wherein a pixel includes:
a plurality of transistors [fig. 4 @T1 and T2] connected to the data line [fig. 4 @D], the write scan line [fig. 4 @S1]; and
a light emitting element [fig. 4 @OLED] connected to a corresponding transistor [fig. 4 @T2] among the transistors, and wherein
the two sub-bias scan lines [fig. 18 @portion of 42 left of K2 and 42 right of K2] are disposed in a same layer [fig. 18 illustrates each of transistor gates formed in the second conductive layer illustrated in fig. 18] as gate electrodes of the transistors [¶0155, T1 gate is fig. 18 @41-1, T2 gate is fig. 18 @41, fig. 18 illustrates second conductive layer], and
the connecting line [fig. 11b @92] is disposed above the gate electrodes [fig. 11b illustrates third conductive layer which is above the second conductive layer] and
wherein in a layer [¶0037, “FIG. 9a and Fig. 9b are schematic diagrams after a pattern of a second conductive layer”] where the sub-bias scan lines [fig. 9b @42] are arranged, conductors are not disposed between the sub-bias scan lines in the first direction [fig. 9b @X, fig. 9b illustrates the claimed structure]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of providing display scan signal lines comprising unequal widths and through holes and on the same conductive layer as their respective transistor gate electrode, as taught by Feng, into the display device taught by Jiang, in order to reduce parasitic capacitances between the second scan signal line 42, and the first power supply line, the data signal line, and the compensation signal line and simplify connecting the scan lines with their corresponding gate electrodes (Feng: ¶0158).
Allowable Subject Matter
Claims 5-6, 8-10, and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The examiner can normally be reached 1000-1800 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Douglas Wilson/Primary Examiner, Art Unit 2622
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