DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Objections
The following claims are objected to because of the following informalities. Appropriate correction is required.
Claim 1 should be amended to “wherein the frequently accessed regions i) are associated with counters that satisfy a threshold criterion and ii) are further tracked using a filter at a second granularity”. This is to clarify what (frequently access regions or counters) is associated with filter.
Claim 6 should be amended to “wherein counts, associated , are [[are]] stored within one or more address translation tables”. This is to clarify what (count, accesses or plurality of regions) is stored in translation table(s).
Claims, dependent upon above identified claims, are also objected on the same grounds as said above identified claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 5 and 7 – 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Simionescu (US 20210089454).
Regarding claim 1, Simionescu teaches
A memory buffer device (memory buffer device = Fig. 1 controller 115 with cache manager 113) coupled to a device memory (device memory = Fig. 1 memory device 140) comprising a plurality of regions, (Simionescu teaches controller 115 connected (coupled) to memory device 140 (see Fig. 1) wherein controller 115 includes buffer memory (buffer memory) (see ¶[28]).)
wherein the memory buffer device identifies frequently accessed regions of the plurality of regions [by counting accesses to the plurality of regions at a first granularity],
wherein the frequently accessed regions are associated with counters that satisfy a threshold criterion and are further tracked using a filter at a second granularity, (claim objection: This limitation should read “wherein the frequently accessed regions i) are associated with counters that satisfy a threshold criterion and ii) are further tracked using a filter at a second granularity”)
wherein the second granularity is smaller than the first granularity (Simionescu teaches cache manager 113 (see ¶[57]) tracking access statistics (counters, filter) of segments of data (plurality of regions), in memory device 140, that have first granularity (second granularity) wherein said access statistics are rate (counting) of accesses (accesses) to said segments of data such as how often (frequently) said segments of data (regions of the plurality of regions) are accessed (accessed) (see Fig. 2, ¶[59]). Simionescu also teaches based on said access statistics (counters) satisfying a threshold criterion (threshold criterion), a segment of said segments of data is updated, by cache manager 113 (see ¶[57]), from said first granularity to second granularity (first granularity) and wherein said second granularity (first granularity) > said first granularity (second granularity) (see Fig. 2, ¶[60]). Note that said access statistics (counters) tracks said segment (region) of said segments of data (plurality of regions) used to form a page having said second granularity (see ¶[62]) and there are plural pages (plurality) (see ¶[38]). As such, there are plural of said segment being tracked by said access statistics.)
Regarding claim 2, Simionescu teaches the memory buffer device of claim 1 where Simionescu also teaches
wherein accesses to the plurality of regions at the first granularity are tracked for a first duration and accesses to the frequently accessed regions at the second granularity are tracked for a second duration (Simionescu teaches tracking access statistics of segments of data (plurality of regions) wherein said access statistics are rate of accesses (accesses) of said segments of data having first granularity (second granularity) where upon said access statistics satisfying a threshold criterion, a segment of said segments of data is updated to second granularity (first granularity) (see Fig. 2, ¶[59-60]) wherein said segment (region) is used to form a page having said second granularity (see ¶[62]) and there are plural (plurality) pages (see ¶[38]). Note that said segments of data, having said first granularity (second granularity) is tracked before (second duration) said access statistics satisfying said threshold criterion and subset of said segment of data, having said second granularity (first granularity), is tracked after (first duration) after said access statistics satisfying said threshold criterion.)
Regarding claim 3, Simionescu teaches the buffer device of claim 2 where Simionescu also teaches
wherein the first duration and the second duration are different (Simionescu already teaches in claim 2, first duration and second duration are different. In claim 2, segments of data (plurality of regions), having first granularity (second granularity) are tracked before (second duration) access statistics satisfies threshold criterion and subset of said segments of data, having second granularity (first granularity), are tracked after (first duration) said access statistics satisfies said threshold criterion. Note that these two durations are different (one is before threshold and one is after).)
Regarding claim 5, Simionescu teaches the memory buffer device of claim 1 where Simionescu also teaches
wherein at least a portion of at least one frequently accessed region tracked at the second granularity is cached by the memory buffer device (Simionescu teaches tracking access statistics of segments of data (plurality of regions, at least a portion of at least one frequently accessed region), stored in memory device 140, at first granularity (second granularity) wherein i) said access statistics is how often (frequently) said segments of data are accessed (accessed) and ii)said segments of data are sectors (see ¶[59]). Simionescu also teaches said sectors (with accesses exceeding threshold) are moved (cached) from sector cache to page cache by cache manager 113 (see ¶[53]) in controller 115 (memory buffer device) (see Fig. 1).)
Regarding claim 7, Simionescu teaches the memory buffer device of claim 1 where Simionescu also teaches
wherein counting accesses to the plurality of regions at the first granularity is responsive to a memory request satisfying a counting criterion (Examiner is interpreting “memory access request satisfying a counting criterion” to refer to memory request from first host of plurality of hosts (see claim 8).) (Simionescu teaches tracking access statistics of segments of data (plurality of regions) at first granularity where said access statistics is rate (counting) of accesses (accesses) to said segments of data, an upon (responsive to) said access statistics reaching a threshold criterion, updating a segment of said segments of data from said first granularity to second granularity (first granularity) wherein said segment is used to form a page (see Fig. 2, ¶[59-62]) there are plural pages (plurality) (see ¶[38]). Note that said access statistics is rate of accesses (accesses) to said segments of data which are sectors (see ¶[59]) that are accessed by (from) host system (first host) (see ¶[48]) via memory access operation (memory request) (see ¶[15]). As such, said updating (of said segment to said second granularity) is upon (responsive to) accesses from said host system via said memory access operation. Simionescu also teaches there are plural of said host system (plurality of hosts) (see ¶[77]).)
Regarding claim 8, Simionescu teaches the memory buffer device of claim 7 where Simionescu also teaches
wherein the counting criterion comprises at least one of:
[the memory request is for an address within a range of counting addresses;]
the memory request is from a first host of a plurality of hosts; or (Simionescu already teaches in claim 7, memory request satisfying counting criterion)
[the memory request is for an address associated with a first virtual machine of a plurality of virtual machines]
Regarding claim 9, Simionescu teaches the memory buffer device of claim 1 where Simionescu also teaches
wherein the memory buffer device is part of at least one of:
a memory module; or (Simionescu teaches controller 115 (memory buffer device) is part of memory sub-system 110 (see Fig. 1) that is a memory module (memory module) (see ¶[19]).)
[a compute express link (CXL) module]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Simionescu in view of Yang (US 20210406198).
Regarding claim 4, Simionescu teaches the memory buffer device of claim 1 where access statistics (filter) tracks accesses to frequently accessed regions at second granularity (see claim 1) but does not appear to explicitly teach using bloom filter or counting bloom filter to track said accesses.
However, Yang teaches using counting bloom filter (counting bloom filter) (which is a variant of bloom filter (bloom filter) (see Yang ¶[61])) to track access operations over varying time periods (see Yang ¶[73]).
In view of Yang, Simionescu is modified such that said access statistics (tracking accesses to frequently accessed regions at second granularity) is performed using counting bloom filter (counting bloom filter) which is a variant of bloom filter (bloom filter).
Simionescu and Yang are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Simionescu in the manner described supra because counting bloom filter extends bloom filter capability to be able to report how many times an element has been addressed (Yang, ¶[61]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Simionescu in view of Kaneko (US 20220283741).
Regarding claim 6, Simionescu teaches the memory buffer device of claim 1 and
counts associated with accesses to the plurality of regions at the first granularity (Simionescu teaches tracking access statistics of segments of data (plurality of regions), in memory device 140, that have first granularity wherein said access statistics are rate (counts) of accesses (accesses) to said segments of data (see Fig. 2, ¶[59]). Simionescu also teaches based on said access statistics satisfying a threshold criterion, a segment of said segments of data is updated from said first granularity to second granularity (first granularity) (see Fig. 2, ¶[60]). Note that said access statistics (counters) tracks said segment (region) of said segments of data (plurality of regions) used to form a page having said second granularity (first granularity) (see ¶[62]) and there are plural pages (plurality) (see ¶[38]). As such, there are plural of said segment being tracked by said access statistics.)
Simionescu teaches a base device that counts accesses to plurality of regions at first granularity (see claim 6). The claimed invention improves upon said base device by storing said counts in address translation table(s) (see also limitation below).
wherein counts associated with accesses to the plurality of regions at the first granularity are stored within one or more address translation tables
This improvement to said base method is an application of known technique from Kaneko – translation table (address translation table) (storing correspondence between logical addresses and physical addresses) stores (within) write count information of each page (see Kaneko Fig. 6, ¶[43]) wherein said write count is number (counts) of write operations (accesses) (see Kaneko Fig. 6, ¶[46]).
One of ordinary skill in the art would recognize that this known technique of using address translation table to store one type of operation count can also be applied to store another type of operations count, and the result would have been predictable. In this instance, said counts of accesses (to plurality of regions at first granularity) is stored in address translation table that stores correspondence between logical addresses and physical addresses. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Kaneko’s known technique would have yielded i) predictable result of said counts of accesses (to plurality of regions at first granularity) being stored in address translation table that stores correspondence between logical addresses and physical addresses, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Allowable Subject Matter
Claim 10 recites, at least, using first filter, tracking accesses to regions, to determine frequently accessed subset of said regions where a second filter is used to track accesses to said subset of regions. This subject matter is reflected in the following limitations of claim 10.
wherein the first filter tracks memory accesses to the plurality of regions, and wherein the second filter tracks memory accesses to a subset of the plurality of regions identified as frequently accessed by the first filter
Simionescu teaches using access statistics (first filter), tracking rate of accesses (memory accesses) to segments of data (plurality of regions) having a first granularity, to change a segment (subset) of said segments of data to a second granularity that is larger than said first granularity wherein said change is based on said access statistics having rate of accesses (frequently accessed) exceeding threshold (see Simionescu Fig. 2, ¶[59-60]). However, Simionescu does not appear to explicitly teach using a second filter to track accesses to said segment. Therefore, claim 10 is allowable over Simionescu.
Muchherla (US 20210191815) teaches when a block is not recently written, switching from using physical block level read counters (first filter), to track number of read operations (memory accesses) performed on respective one of blocks (plurality of regions), to super block level read counters (second filter) to track number of read operations (memory accesses) performed on respective super blocks (subset) comprising plural blocks (see Muchherla Fig. 2-3, ¶[33-34]). Note that Muchherla teaches using said super block level read counters (second filter) when block is not recently written (i.e. not frequently accessed) whereas claim 10 requires that said block be frequently accessed. Therefore, claim 10 is allowable over Muchherla.
Muchherla also teaches i) using super block level read counters (first filter) to track number of read operations (memory accesses) performed on respective super blocks (comprising plural blocks (plurality of regions) (see Muchherla ¶[20])) and ii) when age indicates that a block is recently written (frequently accessed), using physical block level read counters (second filter) to track number of read operations (memory accesses) performed on respective one of blocks (subset of plurality of regions) (see Muchherla Fig. 2-3, ¶[33-35]) where Jones (US 6421766) teaches that said age is based on said physical block level read counters (see Jones col 2 ln 30-35). Since Muchherla teaches deleting corresponding physical block level read counters of a first super block that uses super block level read counter (first filter) (see Muchherla Fig. 2 step 250 and corresponding paragraphs), there is no said corresponding physical block level read counters available to identify block, in said first super block, that is recently written in order to use said physical block level read counters. Therefore, claim 10 is allowable over Muchherla and Jones.
Claim 17 is the memory module claim corresponding to memory buffer claim 10, and is considered allowable for the same reasons as claim 10.
Claims, dependent upon independent claims 10 or 17, are also allowable over prior art for the same reasons as said independent claims.
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139