Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendment, filed 06/24/2026, has been received, entered into the record, respectfully and fully considered.
By this amendment, Claim 14 have been amended. Thus, claims 1-20 have been examined.
Any objection, claim interpretation and claim rejection not repeated below is withdrawn due to Applicant's amendments.
Response to Arguments
Applicant's arguments filed 06/24/2026 have been fully considered and have been addressed as follows. Applicant’s arguments include portions “a” and “b,” each being recited below and responded briefly.
a. Applicant argued on page 6 of the remarks:
Paragraph [0024] describes generation of GTP relative to the circuitry shown in FIG. 1 as an example of the claimed internal global timing pulse (claim 10) and internal clock pulse (claims 11-20), timing diagrams shown in FIGS. 2A and 2B show the timing of GTP, and other paragraphs further discuss generation of GTP.
In response to Applicant’s Argument “a,” Examiner would like to clarify and point out that Spec [0032] states “The output of the tristate inverter (e.g., CTR) plays a crucial role in generating the global timing pulse (GTP) used for internal clock generation”. Examiner notes that GTP is used to generate internal clock, could be interpreted as GTP is an input and internal clock is an output, i.e., “the global timing pulse” is not same as “internal clock pulse”, which is conflict with [0020] - "internal clock pulse (e.g., global timing pulse (GTP) generation circuitry." i.e. internal clock pulse is the same as GTP.
b. Applicant argued on page 11-17 of the remarks in regarding Claim Rejections - 35 USC §103:
Applicant’s arguments with respect to claim(s) 1, 11 and 18 have been considered but are moot because the newly referred prior art JAIN et al. US 20250277850.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11 line 6 and Claim 18 line 6 recite “an internal clock pulse”, as indicated in [0032], it states “The output of the tristate inverter (e.g., CTR) plays a crucial role in generating the global timing pulse (GTP) used for internal clock generation”. [0016] The term "global timing pulse (GTP) signal" (GTP) signal refers to a generated internal clock signal (e.g., internal clock pulse) .... [0020] states "internal clock pulse (e.g., global timing pulse (GTP) generation circuitry." i.e. internal clock pulse is the same as GTP. It is conflict and unclear whether "global timing pulse (GTP) signal" or “the internal clock pulse” are the same or not.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
For claim 1, a tristate inverter, a reset circuitry and a clamp circuitry are not interrelated.
Any claim not specifically mentioned above, is rejected due to its dependency on the rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, and 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saint-Laurent et al., US 20070300108, hereinafter Saint-Laurent, in view of JAIN et al. US 20250277850, hereinafter JAIN’850.
As per claim 1, Saint-Laurent teaches A circuit comprising:
a tristate inverter; ([0035] the tri-state inverter 218)
a reset circuitry; and
([0045] tristate inverter 234 or tristate inverter 236 can be replaced by another tristate logic gate to implement an asynchronous set or reset function for the master latch. …… reset function can be implemented in the slave latch by replacing inverter 280 or tristate inverter 282)
EXCEPT
a clamp circuitry, wherein the clamp circuitry is configured for design-for-test (DFT)-mixing.
JAIN’850 teaches
a clamp circuitry, wherein the clamp circuitry is configured for design-for-test (DFT)-mixing. (Fig. 7, [0115]; Fig. 6 622, 632;)
Saint-Laurent and JAIN’850 are analogous art as both are in the field of design for test, It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Saint-Laurent to incorporate the teaching of the clamp circuitry from JAIN’850 as indicated above, in order to improve a test logic. (Saint-Laurent, [0009]).
As per claim 11, Saint-Laurent teaches A method comprising:
in a test mode, providing a DFT information signal (Fig.2 228) to a circuit;
([0036] In a test mode, the shift value is "1" (a logic high, such as a level that is above a threshold voltage level, for example) at the shift input 208, the tri-state inverter 218 is enabled and the scan test input 209 is connected to the second state node 228 via the tri-state inverter 218.
Fig.3, [0011], receiving a mode selection input to select between a test mode and an operating mode and selectively generating a first clock or a second clock based on the mode selection input.)
EXCEPT
in response to receiving a clock signal at a clamp circuitry of the circuit, retaining the DFT information signal at the clamp circuitry; and
in response to a transition of the clock signal, deactivating the clamp circuitry and generating an internal clock pulse.
JAIN’850 teaches
in response to receiving a clock signal at a clamp circuitry of the circuit, retaining the DFT information signal at the clamp circuitry; and
in response to a transition of the clock signal, deactivating the clamp circuitry and generating an internal clock pulse.
(Fig. 7, [0115]; Fig. 6 622, 632;)
Saint-Laurent and JAIN’850 are analogous art as both are in the field of design for test, It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Saint-Laurent to incorporate the teaching of the clamp circuitry from JAIN’850 as indicated above, in order to improve a test logic. (Saint-Laurent, [0009]).
As per claim 18, Saint-Laurent teaches A method comprising:
in a functional mode, providing, from a tristate inverter, a capture-test-response (CTR) signal on a critical path of a circuit; (0035] ......when in a functional or operating mode, the tri-state inverter 218 that is coupled to the scan test input 209 is disabled when the shift input 208 receives a shift value of zero ( or a logic low value, such as a level that is below a threshold voltage level, for example). The output of the NOR gate 240 is inverted by inverter 244 and inverted again at the control inputs 251 and 257 of the transmission gate 254, which is enabled to pass data from the data input 250 to the first state node 258.)
EXCEPT
in response to an external clock signal, receiving at a logic circuitry coupled to the critical path, at least the CTR signal; and
generating, by a first stage of the logic circuitry, an internal clock pulse.
JAIN’850 teaches
in response to an external clock signal, receiving at a logic circuitry coupled to the critical path, at least the CTR signal; and
generating, by a first stage of the logic circuitry, an internal clock pulse.
(Fig. 7, [0115]; Fig. 6 622, 632, Clock out;)
Saint-Laurent and JAIN’850 are analogous art as both are in the field of design for test, It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Saint-Laurent to incorporate the teaching of the clamp circuitry from JAIN’850 as indicated above, in order to improve a test logic. (Saint-Laurent, [0009]).
As per claim 2, Saint-Laurent-JAIN’850 teaches the circuit applied as above in claim 1, Saint-Laurent further teaches The circuit applied as claim 1, wherein the DFT-mixing corresponds to at least one of combining or configuring for use both functional and test signals. ([0040]; [0044])
As per claim 8, Saint-Laurent-JAIN’850 teaches the circuit applied as above in claim 1, JAIN’850 further teaches wherein:
the clamp circuitry is configured to receive a clamp control signal, and
the clamp control signal corresponds to an inverse design-for-test (NDFT) clock signal. (Fig.7)
As per claim 9, Saint-Laurent-JAIN’850 teaches the circuit applied as above in claim 1, Saint-Laurent further teaches wherein the tristate inverter is configured to receive a chip-enable (CEN) signal. (Fig.2, the shift input 208; Fig.1, MODE SELECTION 116)
As per claim 10, Saint-Laurent-JAIN’850 teaches the circuit applied as above in claim 1, JAIN’850 further teaches wherein the circuit is configured to generate an internal global timing pulse. (Fig.7, Clock Out)
As per claim 12, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 11, Saint-Laurent further teaches wherein:
the internal clock pulse is based at least partially on the DFT information signal; and
the clock signal is an inverse design-for-test clock signal.
([0031]-[0032])
As per claim 13, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 11, JAIN’850 further teaches further comprising:
in response to the deactivation of the clamp circuitry, generating a feedback signal; and (Fig.5, [0088]; Fig. 7)
Saint-Laurent further teaches
resetting, by a reset circuitry of the circuit coupled to the clamp circuitry, the DFT information signal at the clamp circuitry based on the generated feedback signal. ([0045])
As per claim 14, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 13, Saint-Laurent further teaches wherein generating the feedback signal comprises:
providing, at a logic circuitry of the circuit coupled to the reset circuitry, the DFT information signal and an external clock signal; and
(Fig. 3, 310, a second clock output; [0011], receiving a mode selection input to select between a test mode and an operating mode and selectively generating a first clock or a second clock based on the mode selection input.)
JAIN’850 further teaches
generating, by a first stage of the logic circuitry, the internal clock pulse; and
generating, by a second stage of the logic circuitry, a feedback signal based at least partially on the internal clock pulse.
(Fig.5, [0088]; Fig. 7)
As per claim 15, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 11, JAIN’850 further teaches wherein the internal clock pulse corresponds to a global timing pulse (GTP). (Fig.7, Clock Out)
As per claim 16, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 11, Saint-Laurent further teaches wherein generating the internal clock pulse comprises:
providing, to a logic circuitry of the circuit coupled to the reset circuitry, the DFT information signal and an external clock signal; and
generating, by a first stage of the logic circuitry, the internal clock pulse.
(Fig. 3, 310, a second clock output; [0011], receiving a mode selection input to select between a test mode and an operating mode and selectively generating a first clock or a second clock based on the mode selection input.)
As per claim 17, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 11, Saint-Laurent further teaches further comprising:
deactivating, by a tristate inverter of the circuit, a chip-enable (CEN) signal.
([0035] In one particular embodiment, when in a functional or operating mode, the tri-state inverter 218 that is coupled to the scan test input 209 is disabled when the shift input 208 receives a shift value of zero ( or a logic low value, such as a level that is below a threshold voltage level......).
As per claim 19, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 18, JAIN’850 further teaches comprising:
generating, by a second stage of the logic circuitry, a feedback signal; and
in response to the feedback signal, transitioning the CTR signal from a logical high state to a logic low state.
(Fig.5, [0088]; Fig. 7)
As per claim 20, Saint-Laurent-JAIN’850 teaches the method applied as above in claim 19, JAIN’850 further teaches wherein transitioning the CTR signal comprises reducing the voltage level of the CTR signal from a first voltage potential to a second voltage potential. (Fig.5, [0088]; Fig. 7)
Claim(s) 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saint-Laurent et al., US 20070300108, hereinafter Saint-Laurent, in view of JAIN et al. US 20250277850, hereinafter JAIN’850, in further view of JAIN et al. US 20130003905, hereinafter JAIN’905.
As per claim 3, Saint-Laurent-JAIN’850 teaches the circuit applied as above in claim 1, EXCEPT wherein: the clamp circuitry comprises first and second PMOS devices; and
the clamp circuitry is configured to retain a design-for-test (DFT) information signal at a logic high state.
JAIN’905 teaches wherein: the clamp circuitry comprises first and second PMOS devices; and
(Fig. 4; [0089], error-detection-and-retention circuit 109; [0098] The error-history circuit 430…...a first and second PMOS transistor 433 and 434)
the clamp circuitry is configured to retain a design-for-test (DFT) information signal at a logic high state. ([0095]- [0096])
JAIN’905 is related to transition detector for detecting a data transition within a clock window, may be used to monitor timing and critical parts of applications such as on-chip logic, maybe configured to have self-test mode ([0001]-[0002], [0011]. Saint-Laurent and JAIN’850,are both in the field of design for test. Therefore JAIN’905 Saint-Laurent and JAIN’850 are analogous art as they are all related in the field of chip logic test, It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Saint-Laurent-JAIN’850 to incorporate the teaching of the elements from JAIN’905 as indicated above, in order to improve a test logic. (Saint-Laurent, [0009]).
As per claim 4, Saint-Laurent-JAIN’850-JAIN’905 teaches the circuit applied as above in claim 3, JAIN’905 further teaches wherein:
the first PMOS transistor is configured to receive a clamp control signal; and
the second PMOS transistors is configured to receive a retention mode signal.
([0089] FIG. 4…...the error-detection-and-retention circuit 109; [0096])
As per claim 5, Saint-Laurent-JAIN’850 teaches the circuit applied as above in claim 1, Saint-Laurent further teaches wherein the reset circuitry comprises:
a latch-holding circuitry, and ([0034] When the shift input 208 is at a logic low level, the output of the NAND gate 284 is held at a logic high level.)
a NAND logic circuitry. ([0034] The NAND gate 284; [0045] reset function can be implemented in the slave latch by replacing inverter 280 or tristate inverter 282)
As per claim 6, Saint-Laurent-JAIN’850 teaches the circuit applied as above in claim 5, EXCEPT wherein the latch-holding circuitry comprises an NMOS device.
JAIN’905 teaches
wherein the latch-holding circuitry comprises an NMOS device. ([0081], [0091] The drain node of the second NMOS transistor 423 and the first PMOS transistor 424 may be coupled to form an output 421 to the error-history circuit 430.)
JAIN’905 is related to transition detector for detecting a data transition within a clock window, may be used to monitor timing and critical parts of applications such as on-chip logic, maybe configured to have self-test mode ([0001]-[0002], [0011]. Saint-Laurent and JAIN’850,are both in the field of design for test. Therefore JAIN’905 Saint-Laurent and JAIN’850 are analogous art as they are all related in the field of chip logic test, It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Saint-Laurent-JAIN’850 to incorporate the teaching of the elements from JAIN’905 as indicated above, in order to improve a test logic. (Saint-Laurent, [0009]).
As per claim 7, Saint-Laurent-JAIN’850-JAIN’905 teaches the circuit applied as above in claim 6, JAIN’905 further teaches wherein:
the NMOS device is configured to receive an inverse design-for-test (NDFT) clock signal to prevent a direct current path between the reset circuitry and a first PMOS device of the clamp circuitry. ([0090] first and second NMOS transistors 422 and 423.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Komai et al., US 6069829, INTERNAL CLOCK MULTIPLICATION FOR
TEST TIME REDUCTION
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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