Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 2, 7, 8, 10 – 18, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20250174538).
Regarding claim 1, Lee discloses an electronic device, comprising:
a transparent core substrate (glass core 21, Fig. 8) comprising a through hole (through hole for the via 23),
wherein the transparent core substrate comprises:
a first transparent core layer (first glass 61) comprising a first sub-through hole (the top portion of the through hole for the via 23); and
a second transparent core (the second glass 62) layer bonded to the first transparent core layer (61), wherein the second transparent core layer comprises a second sub-through hole (the bottom portion of the through hole for the via 23), and the first sub-through hole overlaps the second sub-through hole to form the through hole; and
a first buffer layer (layer 223 or 21d inside the through hole; Fig. 5) disposed in at least a part of the through hole.
Regarding claim 2, Lee discloses the claimed invention as set forth in claim 1. Lee further suggests the first sub-through hole has an aperture (the opening of the through hole), the first sub-through hole and the second sub-through hole have an overlapping area (61 overlaps 62), the overlapping area comprises an overlapping width (Fig. 8), and the overlapping width is greater than or equal to 0.5 times the aperture and less than or equal to the aperture (the overlapping width of 61 and 61 is greater than the aperture of the through hole).
Regarding claim 7, Lee discloses the claimed invention as set forth in claim 1. Lee further discloses a conductive via (via 23), a first redistribution layer (upper layer 26), a second redistribution layer (lower layer 29), the conductive via being disposed in the through hole (Fig. 8), wherein the transparent core substrate is disposed between the first redistribution layer and the second redistribution layer, and the first redistribution layer is electrically connected to the second redistribution layer through the conductive via (Fig. 8).
Regarding claim 8, Lee discloses the claimed invention as set forth in claim 1. Lee further suggests the first buffer layer (layer 23d, Fig. 5) is disposed in the first sub-through hole, and the electronic device further comprises a second buffer layer (another layer 21d or layer 223 in the via hole) disposed in the second sub-through hole.
Regarding claim 10, Lee discloses the claimed invention as set forth in claim 1. Lee further suggests a polymer layer (the insulation layer 223) disposed in the through hole, wherein the polymer layer is disposed between the first buffer layer and the transparent core substrate.
Regarding claim 11, Lee discloses the claimed invention as set forth in claim 1. Lee further suggests each of the first transparent core layer and the second transparent core layer comprises a glass substrate (glass layer 61 and 62).
Regarding claim 12, Lee discloses the claimed invention as set forth in claim 1. Lee further suggests in a cross-sectional view of the electronic device, the first sub-through hole has hourglass shape (the hourglass of the via 23, Fig. 8).
Regarding claim 13, Lee discloses a manufacturing method of an electronic device, comprising:
forming a transparent core substrate (the glass core 21, Fig. 8) and a first buffer layer (layer 223 or 21d inside the through hole; Fig. 5), wherein the transparent core substrate comprises a through hole (the through hole for the via 23), the first buffer layer is disposed in at least a part of the through hole, and the transparent core substrate comprises: a first transparent core layer (glass core 61) comprising a first sub-through hole (the through hole in glass core 61); and
a second transparent core layer (glass core layer 62) bonded to the first transparent core layer, wherein the second transparent core layer comprises a second sub-through hole (the through hole in layer 62), and the first sub-through hole overlaps the second sub-through hole to form the through hole; and forming a first redistribution layer (the upper layer 26) on a surface of the first transparent core layer away from the second transparent core layer.
Regarding claim 14, Lee discloses the claimed invention as set forth in claim 13. Lee further discloses the first redistribution layer (26) is formed after forming the transparent core substrate and the first buffer layer (form the core substrate 21, then the through hole, then the upper layer 26), and the manufacturing method further comprises forming a conductive via (conductive via 23) in the through hole between forming the transparent core substrate and the first buffer layer and forming the first redistribution layer.
Regarding claim 15, Lee discloses the claimed invention as set forth in claim 14. Lee further suggests forming the transparent core substrate comprises: forming the first transparent core layer (61) and the second transparent core layer (62) separately; and bonding the second transparent core layer to the first transparent core layer through an interposer (the adhesive between layers 61 and 62; paragraph 119).
Regarding claim 16, Lee discloses the claimed invention as set forth in claim 14. Lee further suggests forming a second redistribution layer (the lower layer 29; Fig. 8) on a surface of the second transparent core layer away from the first transparent core layer after forming the first redistribution layer.
Regarding claim 17, Lee discloses the claimed invention as set forth in claim 13. Lee further suggests the first redistribution layer (26) is formed before forming the transparent core substrate (21) and the first buffer layer, and the manufacturing method further comprises disposing at least one electronic unit (30) on the first redistribution layer (26) and forming a protecting layer (60) on the first redistribution layer between forming the first redistribution layer (60) and forming the transparent core substrate (26) and the first buffer layer (223 or 23).
Regarding claim 18, Lee discloses the claimed invention as set forth in claim 17. Lee further suggests forming the transparent core substrate comprises: forming the first transparent core layer (61) comprising the first sub-through hole after forming the first redistribution layer; forming a first sub-conductive via (via 23 in layer 61) and the first buffer layer in the first sub-through hole; forming the second transparent core layer (62) comprising the second sub-through hole (through hole in 62); forming a second sub-conductive via (via 23 in the core substrate 62) and a second buffer layer (layer 223) in the second sub-through hole; and bonding the second transparent core layer to the first transparent core layer through an interposer (the polymer adhesive between layer 61 and 62; paragraph 119), wherein the second sub-conductive via overlaps the first sub-conductive via to form a conductive via (conductive via 23).
Regarding claim 20, Lee discloses the claimed invention as set forth in claim 17. Lee further suggests forming a second redistribution layer (29, Fig. 8) on a surface of the transparent core substrate away from the first redistribution layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20250174538), in view of Kulkarni (US 12080632).
Regarding claim 3, Lee discloses the claimed invention as set forth in claim 1.
Lee does not explicitly disclose an interposer disposed between the first transparent core layer and the second transparent core layer, wherein a thickness of the interposer is greater than or equal to 1 nanometer and less than or equal to 20 nanometers.
Kulkarni suggests an interposer layer (hybrid bond layer 340 include copper; column 5, lines 10 - 11; Fig. 3) disposed between the first transparent core layer (310) and the second transparent core layer (320).
Lee suggests an adhesive layer between two glass layers (paragraph 119). The adhesive layer is thin to the point of almost invisible (Fig. 8).
It would have been obvious to one having skill in the art at the effective filing date of the invention include an adhesive layer in order to attach two glass layers together.
Regarding claim 6, Lee discloses the claimed invention as set forth in claim 1.
Lee does not explicitly disclose an interposer disposed between the first transparent core layer and the second transparent core layer, wherein the interposer includes a material different from a material of the first transparent core layer.
Kulkarni teaches an interposer (hybrid bond layer 340 include copper; column 5, lines 10 - 11; Fig. 3) disposed between the first transparent core layer (310) and the second transparent core layer (320), wherein the interposer includes a material different (bonding layer with copper) from a material of the first transparent core layer (glass).
It would have been obvious to one having skill in the art at the effective filing date of the invention include a bonding layer between two glass layers in order to attach these two layer together to form a complete circuit board.
Claim(s) 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20250174538), in view of Shin (CN 117998737).
Regarding claim 9, Lee discloses the claimed invention as set forth in claim 1.
Lee does not explicitly disclose the first transparent core layer has a first groove, the second transparent core layer has a second groove facing the first groove, wherein the electronic device further comprises an electronic unit disposed in the first groove and the second groove.
Shin suggests the first transparent core layer has a first groove (the opening for component 201), the second transparent core layer has a second groove (the opening for component 202) facing the first groove, wherein the electronic device further comprises an electronic unit (the electronic device comprising component 201 and 202) disposed in the first groove and the second groove.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include the electronic components in the circuit board in order to complete an intended electronic component.
Regarding claim 19, Lee discloses the claimed invention as set forth in claim 18.
Lee does not explicitly disclose forming the first transparent core layer (61) comprises forming a first groove on a surface of the first transparent core layer away from the first redistribution layer, and forming the second transparent core layer comprises forming a second groove on a surface of the second transparent core layer, wherein the manufacturing method further comprises disposing another electronic unit in the second groove, and bonding the second transparent core layer to the first transparent core layer comprises disposing the second groove on the first groove.
Shin suggests forming the first transparent core layer (111, Fig. 6) comprises forming a first groove (the groove containing component 201) on a surface of the first transparent core layer away from the first redistribution layer, and forming the second transparent core layer (112) comprises forming a second groove (the groove containing the component 202) on a surface of the second transparent core layer, wherein the manufacturing method further comprises disposing another electronic unit (202) in the second groove, and bonding the second transparent core layer to the first transparent core layer comprises disposing the second groove on the first groove (Fig. 6).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include the groove or the space for mounting components in order to complete the intended circuitry of the circuit board.
Allowable Subject Matter
Claims 4 – 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 4, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 and 3, a combination of limitations that the interposer has a dissipation factor, and the dissipation factor is greater than or equal to 0.001 and less than or equal to 0.01 at an operating frequency greater than or equal to 10 MHz. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 5, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 and 3, a combination of limitations that a refractive index of the interposer is different from a refractive index of the first transparent core layer. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Duan (US 20250006665) discloses a glass substrate (132, 134, 136; Fig. 1) having buffer layers (140).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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