DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims [1-10] are rejected on the ground of nonstatutory double patenting as being unpatentable over claims [1, 5, 9-10, 11+4, 12 and 14] of U.S. Patent No. [11, 699, 068] . Although the claims at issue are not identical, they are not patentably distinct from each other because Claims [1-10] of the current application are an obvious variant and encompassed by claims [1, 5, 9-10, 11+4, 12 and 14] of U.S. Patent No. [11, 699, 068].
.Claims [1 and 6] are also rejected on the ground of nonstatutory double patenting as being unpatentable over claims [1 and 4] of U.S. Patent No. [12, 165,049] . Although the claims at issue are not identical, they are not patentably distinct from each other because Claims [1 and 6] of the current application are an obvious variant and encompassed by claims [1 and 4] of U.S. Patent No. [12, 165,049]
Below are the tables showing the conflicting claims.
US. 18/929948
US PAT. No. 11, 699, 068
1. An imaging device comprising silicon, wherein the imaging device comprises a plurality of pixels, wherein each of the plurality of pixels comprises: a first circuit configured to generate a first analog signal; and a first arithmetic circuit configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient, so that an output signal is generated.
1. An imaging device comprising a plurality of circuits, wherein the plurality of circuits each comprises: a plurality of pixels each comprising a circuit configured to generate a first signal and a first operation circuit configured to generate a second signal by multiplying the first signal by a weight coefficient; and a second operation circuit configured to perform an arithmetic operation using a plurality of second signals output from the plurality of pixels, wherein the first operation circuit is configured to be supplied with a potential corresponding to the weight coefficient, wherein the second operation circuit is located below the plurality of pixels, and wherein in each of the plurality of circuits, the plurality of pixels are directly connected to the second operation circuit.
2. The imaging device according to claim 1, wherein the first circuit comprises a photoelectric conversion element and a transistor configured to control an output of the first analog signal in accordance with an output signal from the photoelectric conversion element, and wherein a layer comprising the transistor is located over a layer comprising the first arithmetic circuit, and the photoelectric conversion element is located over the layer comprising the transistor.
10. The imaging device according to claim 1, wherein the circuit configured to generate the first signal comprises a photoelectric conversion element and a transistor, wherein the first signal is in accordance with a signal output from the photoelectric conversion element, wherein the transistor is configured to control output of the first signal, wherein a second layer including the transistor is located over a first layer including the first operation circuit, and wherein a third layer including the photoelectric conversion element is located over the second layer.
3. An imaging device comprising silicon, wherein the imaging device comprises a plurality of circuits comprising a plurality of pixels, wherein each of the plurality of pixels comprises: a first circuit configured to generate a first analog signal; and a first arithmetic circuit configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient, so that a second signal is generated; and a second arithmetic circuit configured to perform an arithmetic operation using the second signal output from each of the plurality of pixels.
1. An imaging device comprising a plurality of circuits, wherein the plurality of circuits each comprises: a plurality of pixels each comprising a circuit configured to generate a first signal and a first operation circuit configured to generate a second signal by multiplying the first signal by a weight coefficient; and a second operation circuit configured to perform an arithmetic operation using a plurality of second signals output from the plurality of pixels, wherein the first operation circuit is configured to be supplied with a potential corresponding to the weight coefficient, wherein the second operation circuit is located below the plurality of pixels, and wherein in each of the plurality of circuits, the plurality of pixels are directly connected to the second operation circuit.
4. The imaging device according to claim 3, wherein the first circuit comprises a photoelectric conversion element and a transistor configured to control an output of the first analog signal in accordance with an output signal from the photoelectric conversion element, and wherein a layer comprising the transistor is located over a layer comprising the first arithmetic circuit, and the photoelectric conversion element is located over the layer comprising the transistor.
10. The imaging device according to claim 1, wherein the circuit configured to generate the first signal comprises a photoelectric conversion element and a transistor, wherein the first signal is in accordance with a signal output from the photoelectric conversion element, wherein the transistor is configured to control output of the first signal, wherein a second layer including the transistor is located over a first layer including the first operation circuit, and wherein a third layer including the photoelectric conversion element is located over the second layer.
5. The imaging device according to claim 3, wherein the second arithmetic circuit comprises at least a part of a neural network.
5. The imaging device according to claim 1, wherein the second operation circuit corresponds to at least a part of a neural network.
6. An imaging device comprising silicon, wherein the imaging device comprises a plurality of circuits, wherein each of the plurality of circuits comprises: a plurality of first circuits each comprising a photoelectric conversion element; and a plurality of first arithmetic circuits, wherein each of the first circuits is configured to output a first analog signal in accordance with an output signal from the photoelectric conversion element, and wherein each of the plurality of first arithmetic circuits is configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient.
14. An imaging device comprising a plurality of pixels, each of the plurality of pixels comprising: a circuit configured to generate a first signal; and a first operation circuit configured to generate an output signal by multiplying the first signal by a weight coefficient, wherein the circuit configured to generate the first signal comprises a photoelectric conversion element and a transistor, wherein the first signal is in accordance with a signal output from the photoelectric conversion element, wherein the transistor is configured to control output of the first signal, wherein a second layer including the transistor is located over a first layer including the first operation circuit, wherein a third layer including the photoelectric conversion element is located over the second layer, wherein the first operation circuit is configured to be supplied with a potential corresponding to the weight coefficient, and wherein the first operation circuit is located below the circuit configured to generate a first signal.
7. The imaging device according to claim 6, further comprising: a second arithmetic circuit configured to perform addition or multiplication of a plurality of second signals output from the plurality of first arithmetic circuits; and a third arithmetic circuit configured to determine a third signal output from the second arithmetic circuit.
11. The imaging device according to claim 1, wherein the plurality of circuits each comprises a third operation circuit, and wherein the third operation circuit is configured to determine a third signal output from the second operation circuit.
4. The imaging device according to claim 3, wherein the second operation circuit further comprises a circuit configured to determine a signal output from the circuit configured to execute at least the part of the product-sum operation.
8. The imaging device according to claim 7, further comprising a neural network, wherein the neural network comprises each of the plurality of first arithmetic circuits, the second arithmetic circuit, and the third arithmetic circuit.
12. The imaging device according to claim 11, wherein the first to third operation circuits correspond to at least a part of a neural network.
9. A chip comprising the imaging device according to claim 7.
9. A chip including the imaging device according to claim 1.
10. A chip comprising the imaging device according to claim 5.
9. A chip including the imaging device according to claim 1.
US. 18/929948
12,165,049
1. An imaging device comprising silicon, wherein the imaging device comprises a plurality of pixels, wherein each of the plurality of pixels comprises: a first circuit configured to generate a first analog signal; and a first arithmetic circuit configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient, so that an output signal is generated.
1. An imaging device comprising a plurality of circuits, wherein the plurality of circuits each comprises: a plurality of pixels; and a first circuit configured to perform an arithmetic operation using a plurality of first signals output from the plurality of pixels, wherein the plurality of pixels each comprises: a second circuit configured to generate a second signal; a third circuit configured to retain a potential corresponding to a weight coefficient; and an operation circuit configured to receive the potential corresponding to the weight coefficient and to multiply the second signal by the weight coefficient, so that one of the first signals is generated, wherein the second circuit comprises a first transistor, wherein the third circuit comprises a second transistor and a capacitor, wherein the operation circuit comprises a third transistor, and wherein the operation circuit is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor.
6. An imaging device comprising silicon, wherein the imaging device comprises a plurality of circuits, wherein each of the plurality of circuits comprises: a plurality of first circuits each comprising a photoelectric conversion element; and a plurality of first arithmetic circuits, wherein each of the first circuits is configured to output a first analog signal in accordance with an output signal from the photoelectric conversion element, and wherein each of the plurality of first arithmetic circuits is configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient.
4. An imaging device comprising a plurality of pixels; wherein the plurality of pixels each comprises: a first circuit configured to generate a first signal; a second circuit configured to retain a potential corresponding to a weight coefficient; and an operation circuit configured to receive the potential corresponding to the weight coefficient and to multiply the first signal by the weight coefficient, so that an output signal is generated, wherein the first circuit comprises a first transistor, wherein the first circuit further comprises a photoelectric conversion element, wherein the first transistor is configured to control an output of the first signal in accordance with an output signal from the photoelectric conversion element, wherein the second circuit comprises a second transistor and a capacitor, wherein the operation circuit comprises a third transistor, wherein the operation circuit is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor, and wherein a layer comprising the first transistor is located over a layer comprising the operation circuit, and the photoelectric conversion element is located over the layer comprising the first transistor.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) [1, 3, 5-6 and 10] is/are rejected under 35 U.S.C. 102 (a1) as being anticipated by Horiba (US. Pat. No. 6, 084,981
Reclaim [1], Horiba discloses: an imaging device comprising silicon (see 1 fig. 1, and col 4. Lines 11-18, The original image supplying unit 1 outputs image data of a processing target and is, for example, a measuring unit for measuring or photographing an object in an image diagnosing apparatus for a medical use such as X-ray photographing apparatus, ultrasonic photographing apparatus, X-ray CT apparatus, nuclear medicine imaging apparatus, magnetic resonance imaging apparatus, etc., a video processing apparatus for a broadcasting use, [a digital photographing apparatus with silicon image sensor]), wherein the imaging device comprises a plurality of pixels (see 13 fig. 7, plurality of pixels in the image supply unit), wherein each of the plurality of pixels (13)comprises: a first circuit configured to generate a first analog signal (see col. 2 lines 64-65, the image information can be outputted by dense/light analog values); and a first arithmetic circuit configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient, so that an output signal is generated (see col. 5 lines, 1-5, Reference numeral 25 denotes multipliers each for multiplying the input and the weight coefficient., the arithmetic circuit being the multiplier 25 as depicted in fig. 4).
Reclaim [3], Horiba discloses an imaging device comprising silicon (see 1 fig. 1, and col 4. Lines 11-18, The original image supplying unit 1 outputs image data of a processing target and is, for example, a measuring unit for measuring or photographing an object in an image diagnosing apparatus for a medical use such as X-ray photographing apparatus, ultrasonic photographing apparatus, X-ray CT apparatus, nuclear medicine imaging apparatus, magnetic resonance imaging apparatus, etc., a video processing apparatus for a broadcasting use, [a digital photographing apparatus with silicon image sensor]), wherein the imaging device comprises a plurality of circuits comprising a plurality of pixels (see 13 fig. 7, plurality of pixels in the image supply unit comprise a plurality circuit for perfuming photo electric conversion), wherein each of the plurality of pixels comprises: a first circuit configured to generate a first analog signal (see col. 2 lines 64-65, the image information can be outputted by dense/light analog values); and a first arithmetic circuit configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient , so that a second signal is generated (see col. 5 lines, 1-5, Reference numeral 25 denotes multipliers each for multiplying the input and the weight coefficient., the arithmetic circuit being the multiplier 25 as depicted in fig. 4, [ the input signal being analog signal output from the image supply unit as depicted in fig. 1]); and a second arithmetic circuit configured to perform an arithmetic operation using the second signal output from each of the plurality of pixels (see 26 fig. 4 and col. 5 lines 4-5, . Reference numeral 26 denotes an adder for adding outputs of the multipliers 25).
Reclaim [5], Horiba discloses, wherein the second arithmetic circuit comprises at least a part of a neural network (see 26 fig. 4, is the adder is part of the neural network as depicted in fig. 4).
Reclaim [6], Horiba discloses an imaging device comprising silicon (see 1 fig. 1, and col 4. Lines 11-18, The original image supplying unit 1 outputs image data of a processing target and is, for example, a measuring unit for measuring or photographing an object in an image diagnosing apparatus for a medical use such as X-ray photographing apparatus, ultrasonic photographing apparatus, X-ray CT apparatus, nuclear medicine imaging apparatus, magnetic resonance imaging apparatus, etc., a video processing apparatus for a broadcasting use, [a digital photographing apparatus with silicon image sensor]), wherein the imaging device comprises a plurality of circuits (see 13 fig. 7, plurality of pixels in the image supply unit comprise a plurality circuit for perfuming photo electric conversion), wherein each of the plurality of circuits comprises: a plurality of first circuits each comprising a photoelectric conversion element (see fig. 7 and coll. 13 lines 44-45, a plurality of pixels 13, [ the plurality of pixels perform photoelectric conversion in order to output analog image data]); and a plurality of first arithmetic circuits (see 25 fig. 4, as many as the input data), wherein each of the first circuits is configured to output a first analog signal in accordance with an output signal from the photoelectric conversion element (see col. 2 lines 64-65, the image information can be outputted by dense/light analog values), and wherein each of the plurality of first arithmetic circuits is configured to receive a potential corresponding to a weight coefficient and to multiply the first analog signal by the weight coefficient (see col. 5 lines, 1-5, Reference numeral 25 denotes multipliers each for multiplying the input and the weight coefficient., the arithmetic circuit being the multiplier 25 as depicted in fig. 4).
Reclaim [10], Horiba further discloses a chip comprising the imaging device according to claim 5 (see 1 fig. 1, the image supply unit).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) [11] is/are rejected under 35 U.S.C. 103 as being unpatentable over Horiba (US. Pat. No. 6, 084,981) in view of Ikeda (US. 2016/0343452).
Reclaim [11] Horiba disclose a chip integrated in the mobile unit (see 1 fig. 1 the image supply unit) However Horiba doesn’t seem to explicitly doesn’t seem to a mobile phone integrated in the image supply unit of Horiba.
Nonetheless in the same field of endeavor Ikeda disclose an information processing apparatus as Horiba (see Ikeda 2910 fig. 7b, a smartphone with a camera 2913). Ikeda further discloses a smartphone where a camera and phone are integrated (see fig. 7B).
Hence it would have been obvious to one of ordinary skill in the art to have been motivated to modify Horiba before the effective filing date of the claimed invention, for example by integrating a phone as taught in Ikeda in the image supply unit of Horiba in order to enhance a usability of Horiba’s device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Sugiyama (US. 9, 936, 172) discloses: The signal processor 15 calculates the luminance signal Y and the color-difference signals C1, C2 from a plurality of pixel signals output from the image sensor 13 by the color-difference sequential system, multiplies the color-difference signals C1, C2 by the gain, and calculates the primary color signals R, G, B. The signal processor 15 includes a YC1C2 calculator 21, a C1C2 gain unit 22, and an RGB calculator 23. Col. 9 lines 4-11.
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/AHMED A BERHAN/Primary Examiner, Art Unit 2639