Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2024 is being considered by the examiner.
Claim Objections
Claim 12 are objected to because of the following informalities:
Claim 12 recites “an i+ 1 symbol"”, the extra “”” should be removed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 and claim 8 recites an error correction device comprises a syndrome generation circuit, an error location determination circuit, an error value determination circuit and an error correction circuit,
Referring to FIG. 3, Spec [0064] recites “a decoder 300 may include an error correction device 310 and an RS code decoder 320.”
Referring to FIG. 4A, Spec [0078] recites “an RS code decoder 400 may include a syndrome generation circuit 410, an error location polynomial generation circuit 420, an error location determination circuit 430, an error correction circuit 440, and a data buffer 450.”
It is inconsistent which device, the error correction device or the RS code decoder, comprises “a syndrome generation circuit, an error location determination circuit, an error value determination circuit and an error correction circuit”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 line 7 recites “receive data”, it is unclear if it is the same data as in line 3 “correct data”. In order to further exam on the merits of the claim, the examiner interprets they are the same data.
Claim 12, 5 & 19 line 6 recites “indicating errors”, it is unclear if it is the same errors as in Claim 8, 1 and 15 line 7 from bottom “obtain locations of errors” respectively, In order to further exam on the merits of the claim, the examiner interprets they are the same.
Claim 14 line 7 recites “an RS code decoder”, it is unclear if it is the same decoder as in Claim 14 line 2 “a Reed-Solomon (RS) code decoder”, In order to further exam on the merits of the claim, the examiner interprets they are the same.
Any claim not specifically mentioned above, is rejected due to its dependency on the rejected claim.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5, 8-12 and 19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
[Claim 1] An error correction device comprising:
(a) a syndrome generation circuit configured to receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data that are determined by substituting powers of primitive elements of a Galois field into a reception polynomial based on the data, wherein respective exponents of the powers of respective ones of the primitive elements used to determine the first syndrome, the second syndrome, and the third syndrome sequentially increase, and wherein respective exponents of the powers of respective ones of the primitive elements used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome sequentially increase;
(b) an error location determination circuit configured to determine a coefficient of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determine a coefficient of a second error location polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain locations of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial;
(c) an error value determination circuit configured to predetermine values of the errors in units of two consecutive symbols, based on the first syndrome and the second syndrome; and
(d) an error correction circuit configured to correct the errors included in the data, based on the locations of the errors and the values of the errors.
Claim 1 is ineligible. (Similarly claim 8 and 15)
Claim Interpretation: Under the broadest reasonable interpretation, the terms of the claim are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP 2111.
Step (a) recites “receive data”, the data may be the codeword RCW read from the memory cell array (refer Fig. 4A, para. [0079])
Step (a) recites “output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data that are determined by substituting powers of primitive elements of a Galois field into a reception polynomial based on the data, wherein respective exponents of the powers of respective ones of the primitive elements used to determine the first syndrome, the second syndrome, and the third syndrome sequentially increase, and wherein respective exponents of the powers of respective ones of the primitive elements used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome sequentially increase”, which uses mathematical formulas or equations and mathematical calculations.
(refer Fig. 4A, US 20250226842, para. [0083]-0086], [0083] The syndrome generation circuit 410 may receive the read codeword RCW and calculate a plurality of syndromes. [0084] For example, values of first to Pth syndromes may be calculated as Equation 2 below.
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Step (b) recites “determine a coefficient of …… based on……syndrome…… obtain locations of errors…… based on the first/second error location polynomial”, which uses mathematical formulas or equations and mathematical calculations
(refer Fig. 4A, para. [0090]-[0094], [0090] The error location polynomial generation circuit 420 may generate an error location polynomial Λ(x) used to search for a location of an error included in the read codeword RCW based on the plurality of syndromes. [0091] The error location polynomial generation circuit 420 may be referred to as a key equation solver…… The error location may be obtained by taking a reciprocal of the root of the error location polynomial Λ(x). [0092] The error location determination circuit 430 may calculate error locations based on the error location polynomial;
Fig. 6B, para. [0128] In some embodiments, the error location polynomial generation circuit 521 may determine the coefficient of the first error location polynomial based on Equation 3…… the error location polynomial generation circuit 521 may determine the coefficient of the second error location polynomial based on Equation 4 below.
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Step (c) recites “predetermine values of the errors in units of two consecutive symbols, based on the first syndrome and the second syndrome”, which uses mathematical formulas or equations and mathematical calculations.
(refer Fig. 5, para. [0158] The error value determination circuit 540 may pre-calculate values of errors that data may have in units of two consecutive symbols based on two syndromes. In addition, the error value determination circuit 540 may provide the pre-calculated values of errors to the error correction circuit 550)
Step (d) recites “correct the errors included in the data, based on the locations of the errors and the values of the errors”, which uses mathematical formulas or equations and mathematical calculations
(refer Fig.5, [0181]-[0186], [0181] the error correction circuit 550 may correct the errors included in the data based on the locations of the errors and the values of the errors as shown in Equation 9 below
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[0185] When the value of the i&i+1 error flag signal ei,i+1 is 1, by adding the error value vi of the i-th symbol to the i-th symbol of the read codeword RCW and adding the error value vi+1 of the i+1 symbol to the i+1 symbol of the read codeword RCW, the error correction circuit 550 may output the i-th symbol and the i+1 symbol of the error-corrected codeword CCW.)
Steps (a), (b), (c) and (d) are all recited as being configured by a circuit such as a syndrome generation circuit, an error location determination circuit, an error value determination circuit and an error correction circuit. The recited circuits are recited at a high level of generality, i.e., as a generic computer circuit performing generic computer functions.
Step 1: This part of the eligibility analysis evaluates whether the claim falls within any statutory category. See MPEP 2106.03. The claim recites an error correction device comprising a syndrome generation circuit, an error location determination circuit, an error value determination circuit, an error correction circuit. The claim is directed to a physical device, which is a machine and/or manufacture, and falls within one of the
statutory categories of invention. (Step 1: YES).
Step 2A, Prong One: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04, subsection II, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
As discussed above, the broadest reasonable interpretation of steps (a), (b), (c), and (d) is that those steps fall within the same grouping of abstract ideas (i.e., mathematical concepts), these limitations are considered together as a single abstract idea for further analysis. (Step 2A, Prong One: YES).
Step 2A, Prong Two: This part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception or whether the claim is “directed to” the judicial exception. This evaluation is performed by (1) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (2) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d).
The claim step (a) recites an additional element of “receive data” As explained above, step(a) is claimed at a high level of generality and could describe receiving the codeword RCW read from the memory cell array. The element amounts to mere data gathering. It is necessary to acquire the data in order to use the recited judicial exception to perform the calculation. The “receiving” element does not impose any other meaningful limits on the claim. Therefore, the additional limitation is insignificant extra-solution activity. See MPEP 2106.05(g).
The claim also recites additional element in steps (a)-(d) of “a syndrome generation circuit”, “an error location determination circuit”, “an error value determination circuit”, “an error correction circuit”, Claim 8 only: “a memory device”, “a memory controller”, “a plurality of memory cells” respectively. When determining whether a claim simply recites a judicial exception with the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners may consider: (1) whether the claim recites only the idea of a solution or outcome i.e., the claim fails to recite details of how a solution to a problem is accomplished; (2) whether the claim invokes computers or other machinery merely as a tool to perform an existing process; and (3) the particularity or generality of the application of the judicial exception. See MPEP 2106.05(f). Here, these circuit are used to generally apply the abstract idea (i.e.,
perform the mathematical calculation using the recited mathematical equation) without placing any limitation on how this is accomplished. The claim omits any details as to how these circuits solve a technical problem, and instead recites only the idea of a solution or outcome. Also, the claim invokes these circuits merely as a tool for making the recited mathematical calculation rather than purporting to improve the technology or a computer. See MPEP 2106.05(f). Therefore, the limitation represents no more than mere instructions to apply the judicial exception on a computer. It can also be viewed as nothing more than an attempt to generally link the use of the judicial exception to the technological environment of computers.
The recited generic circuits merely add a generic computer component to perform the steps and therefore fails to provide an improvement to the technology or technical field. See MPEP 2106.05(a). Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application (Step 2A, Prong Two: NO), and the claim is directed to the judicial exception. (Step 2A: YES).
Step 2B: This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. See MPEP 2106.05.
As explained with respect to Step 2A, Prong Two, there are four additional elements. The additional element of “a syndrome generation circuit, an error location determination circuit, an error value determination circuit, an error correction circuit” in limitations (a)-(d) are at best mere instructions to “apply” the abstract ideas, which cannot provide an inventive concept. See MPEP 2106.05(f).
Additional elements (a) was found to be insignificant extra-solution activity in Step 2A, Prong Two, because they were determined to be insignificant limitations as necessary data gathering and outputting. However, a conclusion that an additional element is insignificant extra solution activity in Step 2A, Prong Two should be re-evaluated in Step 2B. See MPEP 2106.05, subsection I.A. At Step 2B, the evaluation of the insignificant extra-solution activity consideration takes into account whether or not the extra-solution activity is well understood, routine, and conventional in the field. See MPEP 2106.05(g). As discussed in Step 2A, Prong Two above, the recitations of “(a) receive data” and “(a) output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome” are recited at a high level of generality. These elements amount to receiving data from memory and are well understood, routine, conventional activity. See MPEP 2106.05(d), subsection II. 9 As discussed in Step 2A, Prong Two above, the recitation of a computer to perform limitations (a), (b), (c) and (d) amounts to no more than mere instructions to apply the exception using a generic computer component. Even when considered in combination, these additional elements represent mere instructions to implement an abstract idea or other exception on a computer and insignificant extra-solution activity, which do not provide an inventive concept. (Step 2B: NO).
Claims 2, similarly claim 9, and 16 recites additional elements “wherein the error location determination circuit is configured to determine the first error location polynomial based on equation
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, and determine the second error location polynomial based on equation
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, wherein
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denotes the primitive element of the Galois field,
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denotes the first error location polynomial,
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denotes the second error location polynomial,
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denotes the first syndrome,
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denotes the second syndrome,
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denotes the third syndrome,
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denotes the fourth syndrome,
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denotes the fifth syndrome,
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denotes the sixth syndrome, and d and f are positive integers and are different from each other.”, which recites additional mathematical formulas or equations, i.e. Mathematical Concepts.
Claim 3, similarly claim 10, and 17 recites additional elements “wherein the second syndrome is same as the fourth syndrome, wherein the third syndrome is same as the fifth syndrome, and wherein the respective exponents of the powers of respective ones of the primitive elements used to determine the first syndrome, the second syndrome, the third syndrome, and the sixth syndrome sequentially increase.” As these additional limitations are all mathematical relationships, it does not recite additional elements that integrate the judicial exception into a practical application, does not recite additional elements that amount to significantly more than the judicial exception.
Claim 4, similarly claim 11, and 18 recites additional elements “wherein the error location determination circuit is configured to determine the first error location polynomial based on equation
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and determine the second error location polynomial based on equation
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, wherein
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denotes the primitive element of the Galois field,
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denotes the first error location polynomial,
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denotes the second error location polynomial,
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denotes the first syndrome,
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denotes the second syndrome,
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denotes the third syndrome, and
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denotes the sixth syndrome.”, i.e. recites additional mathematical formulas or equations - Mathematical Concepts.
Claim 5, similarly claim 12, and 19 recites additional elements “ wherein the first error location polynomial and the second error location polynomial are polynomials relating to a power of the primitive element of the powers of the primitive elements of the Galois field having an exponent
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of the respective exponents of the powers….”, “when the primitive element having the exponent determines that a value of the first error location polynomial and a value of the second error location polynomial are 0.” As these additional limitations are all mathematical relationships, it does not recite additional elements that integrate the judicial exception into a practical application, does not recite additional elements that amount to significantly more than the judicial exception.
Claim 5, similarly claim 12, and 19 further recites additional elements “wherein the error location determination circuit is configured to output an error flag signal indicating errors in an i-th symbol and an i+1 symbol”, it is mere data gathering and output recited at a high level of generality, and thus are insignificant extra-solution activity. See MPEP 2106.05(g) (“whether the limitation is significant”). In addition, all uses of the recited judicial exceptions require such data gathering and output, and, as such, these limitations do not impose any meaningful limits on the claim. These limitations amount to necessary data gathering and outputting. See MPEP 2106.05.
Claims 9-11 have the same claim as claim 2-4 respectively, thus the same 101 rejection analysis as claim 2-4 respectively applied.
Claims 16-18 are the method claim of claim 2-4, have the same claim as claim 2-4 respectively, thus the same 101 rejection analysis as claim 2-4 respectively applied.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-8, 12-15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Im et al., US 5971607, hereinafter Im, in view of Chen et al., US 10715180, hereinafter Chen.
As per claim 1, Im teaches An error correction device comprising:
a syndrome generation circuit configured to receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data that are determined by substituting powers of primitive elements of a Galois field into a reception polynomial based on the data, wherein respective exponents of the powers of respective ones of the primitive elements used to determine the first syndrome, the second syndrome, and the third syndrome sequentially increase, and wherein respective exponents of the powers of respective ones of the primitive elements used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome sequentially increase; (1:64-2:10 As a first error correcting step, syndromes S.sub.0, S.sub.1, . . . , S.sub.2T-1 are calculated from a received codeword polynomial r(X), i.e., an (N-1)st order polynomial representing the received codeword......Specifically, if substituting a power of the primitive element, .alpha..sup.-j, for a variable X in the error locator polynomial .sigma.(X) results in 0 (i.e., .alpha..sup.-j becomes a root of .sigma.(X)), it means that an error has occurred in r.sub.j, i.e., (N-j)th symbol of a codeword.
1:43-45, If roots of the generator polynomial g(X) of the RS code are 2T consecutive powers of a as in Eq. (1), T being a predetermined positive integer, as many as T errors can be corrected)
an error location determination circuit configured to determine a coefficient of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determine a coefficient of a second error location polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain locations of errors included in the data (2:4-10, 1:43-45)
an error value determination circuit configured to predetermine values of the errors (2:11-12, As a fourth step, error values are calculated by using the error locations and the syndromes.)
an error correction circuit configured to correct the errors included in the data, based on the locations of the errors and the values of the errors. (2:35-37, After finding the error values, the original codeword can be recovered by adding the error values to the corresponding symbols.)
EXCEPT
Chen teaches
(Chen, 7:40-60)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Im to incorporate the teaching of from Chen as indicated above, in order to reduce the decoding time.(Chen, 3:20)
As per claim 5, Im-Chen teaches The error correction device above in claim 1, Im further teaches The error correction device of claim 1,
wherein the first error location polynomial and the second error location polynomial are polynomials relating to a power of the primitive element of the Galois field of the powers of the primitive elements having an exponent
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of the respective exponents of the powers, (1:43-45, If roots of the generator polynomial g(X) of the RS code are 2T consecutive powers of a as in Eq. (1), T being a predetermined positive integer, as many as T errors can be corrected)
Chen further teaches
wherein the error location determination circuit is configured to output an error flag signal indicating errors in an i-th symbol and an i+1 symbol when the primitive element having the exponent determines that a value of the first error location polynomial and a value of the second error location polynomial are 0.
(6:20-26, The output port 116 is communicatively coupled to the second decision unit 114 and configured to abandon the decoding and send an error indicator if none of the N symbols in any of k subtracted first RS syndromes Sxd[0:n−k−1] equals each other.)
As per claim 6, Im-Chen teaches The error correction device applied above in claim 1, Chen further teaches further comprising:
a re-syndrome generation circuit configured to receive error-corrected data, determine a plurality of syndromes for the error-corrected data to determine whether an error correction operation is successful, and output a signal indicating termination of the error correction operation of a Reed-Solomon (RS) code decoder when the error correction operation is successful.
(7:17, The second RS syndrome generator 126; 6:20-26, The output port 116 is communicatively coupled to the second decision unit 114 and configured to abandon the decoding and send an error indicator if none of the N symbols in any of k subtracted first RS syndromes Sxd[0:n−k−1] equals each other.
15:33-36, send an error indicator if none of the N symbols in any of k subtracted first RS syndromes equal each other as determined in block 514.)
As per claim 7, Im-Chen teaches The error correction device applied above in claim 1, Chen further teaches further comprising:
a re-syndrome generation circuit configured to receive error-corrected data, determine a plurality of syndromes for the error-corrected data to determine whether an error correction operation is successful, and output a signal indicating start of the error correction operation of a Reed-Solomon (RS) code decoder when the error correction operation fails.
(7:17, The second RS syndrome generator 126; 6:20-26, The output port 116 is communicatively coupled to the second decision unit 114 and configured to abandon the decoding and send an error indicator if none of the N symbols in any of k subtracted first RS syndromes Sxd[0:n−k−1] equals each other.
15:33-36, send an error indicator if none of the N symbols in any of k subtracted first RS syndromes equal each other as determined in block 514.)
Claims 8, 12-14 have the same claim as claim 1, 5-7 respectively, in a memory system, thus they are rejected under the same reason as indicated above.
Claims 15, 19-20 are the method claim of claim 1, 5-6 respectively, thus they are rejected under the same reason as indicated above.
Examiner’s Notes
Claims 2-4, 16-18 are under 101 and 112(a) rejection, claims 9-11 are under 101, 112(a) and 112 (b) rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Smelser et al., US 5099484, Multiple Bit Error Detection And Correction System Employing A Modified Reed-Solomon Code Incorporating Address Parity And Catastrophic Failure Detection
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RONG TANG whose telephone number is (469)295-9106. The examiner can normally be reached Monday - Friday 7:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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