Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-11 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ang, US 7949916, hereinafter Ang, in view of Saxena et al., US 10107859, hereinafter Saxena.
As per claim 1, Ang teaches A chip testing method, comprising:
(Fig.1, 7:31 programmable elements 20) to generate a first test signal; and
(Fig. 6, 7:26-36, Tester 66 may be a tool such as an automatic test pattern generation (ATPG) tool that applies test data of various patterns to test circuit 10. The test data may include test configuration data (e.g., to configure a programmable integrated circuit to implement test logic) and test vectors. Test configuration data may be loaded into programmable elements 20. Test vectors may be applied to input-output pins 14. Test data may also be loaded into scan chain registers. Test control signals (e.g., scan enable signals and other control signals) may be applied to scan chain circuitry and other circuitry in integrated circuit 10 during testing. Fig. 5, 7:51-67)
(Fig. 15, 13:25-27, Scan circuitry 212 that may be used to perform at-speed delay fault tests in integrated circuit 10 ……
EXCEPT
during the chip probe testing
Saxena teaches
during the chip probe testing
(3:46-51, For example, a first device interface board 44 may be used for probing, the first device interface board 44 having appropriate probing needles to test pins on the wafer;)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Ang to incorporate the teaching of the limitation indicated above from Saxena as indicated above, in order to do effective transition fault testing (Saxena, 3:30).
As per claim 11, Ang teaches A chip, comprising:
a memory circuit configured to store a code;
a processor circuit configured to execute the code
(Fig. 6, 7:26-36, Tester 66 may be a tool such as an automatic test pattern generation (ATPG) tool that applies test data of various patterns to test circuit 10. The test data may include test configuration data (e.g., to configure a programmable integrated circuit to implement test logic) and test vectors. Test configuration data may be loaded into programmable elements 20. Test vectors may be applied to input-output pins 14. Test data may also be loaded into scan chain registers. Test control signals (e.g., scan enable signals and other control signals) may be applied to scan chain circuitry and other circuitry in integrated circuit 10 during testing. Fig. 5, 7:51-67)
a first circuit coupled to the processor circuit via a bus circuit and configured to perform a transition delay fault test in response to the first test signal
(Fig. 15, 13:25-27, Scan circuitry 212 that may be used to perform at-speed delay fault tests in integrated circuit 10 ……
EXCEPT
during the chip probe testing
Saxena teaches
during the chip probe testing
(3:46-51, For example, a first device interface board 44 may be used for probing, the first device interface board 44 having appropriate probing needles to test pins on the wafer;)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Ang to incorporate the teaching of the limitation indicated above from Saxena as indicated above, in order to do effective transition fault testing (Saxena, 3:30).
As per claim 17 , Ang-Saxena teaches The chip applied above in claim 11, Ang teaches further wherein the code comprises a program code executed by the processor circuit during a boot process. (4:31-34)
As per claim 18, Ang-Saxena teaches The chip applied above in claim 11, Ang teaches further wherein the memory circuit is a read-only memory circuit. (4:31-34)
As per claim 19, Ang-Saxena teaches The chip applied above in claim 11, Saxena teaches further comprising:
a second circuit configured to perform the transition delay fault test in response to a second test signal during the chip probe testing,
wherein the processor circuit is further configured to execute a test code in the code to generate the second test signal during the chip probe testing, and one of the first circuit and the second circuit does not access another one of the first circuit and the second circuit.
(3:46-51, For example, a first device interface board 44 may be used for probing, the first device interface board 44 having appropriate probing needles to test pins on the wafer; a second device interface board 44 may be used for final test, the second device interface board 44 having appropriate sockets to test leads on the separate integrated chips.)
As per claim 20, Ang-Saxena teaches The chip applied above in claim 19, Saxena teaches further wherein the second circuit comprises a static random-access memory circuit. (14:56-63)
Claim(s) 2-4, and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ang, US 7949916, hereinafter Ang, in view of Saxena et al., US 10107859, hereinafter Saxena, in further view of Nadeau-Dostie et al., US 20230110161, hereinafter Nadeau-Dostie et al., US 20230110161.
As per claim 2, Ang-Saxena teaches The chip testing method applied above in claim 1, Saxena teaches further comprising: during the chip probe testing, (3:46-51, For example, a first device interface board 44 may be used for probing, the first device interface board 44 having appropriate probing needles to test pins on the wafer;)
EXCEPT
utilizing the first test signal to perform the transition delay fault test on an asynchronous circuit in the chip,
wherein the asynchronous circuit is coupled between the first circuit and a second circuit in the chip, and the first circuit is configured to access the second circuit via the asynchronous circuit in response to the first test signal.
Nadeau-Dostie teaches
utilizing the first test signal to perform the transition delay fault test on an asynchronous circuit (Fig.9 Interfacing circuit 900) in the chip,
wherein the asynchronous circuit is coupled between the first circuit and a second circuit in the chip, and the first circuit is configured to access the second circuit via the asynchronous circuit in response to the first test signal.
(Fig. 9; [0007])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Ang-Saxena to incorporate the teaching of the limitation indicated above from Nadeau-Dostie as indicated above, in order to do effective transition fault testing (Saxena, 3:30).
As per claim 12, Ang-Saxena teaches The chip testing method applied above in claim 11, Saxena teaches further
EXCEPT comprising:
a second circuit; and
an asynchronous circuit coupled between the first circuit and the second circuit,
wherein the processor circuit is further configured to utilize the first test signal to perform the transition delay fault test on the asynchronous circuit
Nadeau-Dostie teaches comprising:
a second circuit; and
an asynchronous circuit (Fig.9 Interfacing circuit 900) coupled between the first circuit and the second circuit,
wherein the processor circuit is further configured to utilize the first test signal to perform the transition delay fault test on the asynchronous circuit
(Fig. 9; [0007])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Ang-Saxena to incorporate the teaching of the limitation indicated above from Nadeau-Dostie as indicated above, in order to do effective transition fault testing (Saxena, 3:30).
As per claim 13, Ang-Saxena-Nadeau-Dostie teaches The chip applied above in claim 12, Nadeau-Dostie teaches further wherein the first circuit is configured to operate according to a first clock signal, the second circuit is configured to operate according to a second clock signal, the asynchronous circuit is configured to operate according to the first clock signal and the second clock signal, and the first clock signal and the second clock signal are asynchronous. (Fig. 9; [0007])
As per claim 14, Ang-Saxena-Nadeau-Dostie teaches The chip applied above in claim 13, Nadeau-Dostie teaches further wherein the first clock signal and the second clock signal come from different clock sources, or a frequency of one of the first clock signal and the second clock signal is not an integer of a frequency of another one of the first clock signal and the second clock signal. (Fig. 9; [0007])
Claim(s) 5-6, and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ang, US 7949916, hereinafter Ang, in view of Saxena et al., US 10107859, hereinafter Saxena, in further view of Pal et al.,US 20170010320, hereinafter Pal.
As per claim 5, Ang-Saxena teaches The chip testing method applied above in claim 2, Saxena teaches further comprising: during the chip probe testing
EXCEPT
Pal teaches
([0031] FIG. 1, ….. Clock domain 112 is connected to clock generation circuit 126. A second clock source 114 is also connected to clock generation circuit 126 and also to internal clock generator 116. Second clock source 114 is also connected to third clock source 120. Internal clock generator 116 is connected to second clock domain 122. Third clock source 120 is connected to third clock domain 124; [0027])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Ang-Saxena to incorporate the teaching of the limitation indicated above from Pal as indicated above, in order to do effective transition fault testing (Saxena, 3:30).
As per claim 6, Ang-Saxena-Pal teaches The chip testing method applied above in claim 5, Pal teaches further wherein each of the first clock signal, the second clock signal, and the third clock signal is a full-speed clock signal during the chip probe testing. ([0031] FIG. 1, ….. Clock domain 112 is connected to clock generation circuit 126. A second clock source 114 is also connected to clock generation circuit 126 and also to internal clock generator 116. Second clock source 114 is also connected to third clock source 120. Internal clock generator 116 is connected to second clock domain 122. Third clock source 120 is connected to third clock domain 124; [0027])
As per claim 15, Ang-Saxena teaches The chip applied above in claim 12, Saxena teaches further comprising: during the chip probe testing
EXCEPT further comprising:
a first clock generator circuit configured to generate a first clock signal
a second clock generator circuit configured to generate a second clock signal
a third clock generator circuit configured to generate a third clock signal
Pal teaches further comprising:
a first clock generator circuit configured to generate a first clock signal
a second clock generator circuit configured to generate a second clock signal
a third clock generator circuit configured to generate a third clock signal
([0031] FIG. 1, ….. Clock domain 112 is connected to clock generation circuit 126. A second clock source 114 is also connected to clock generation circuit 126 and also to internal clock generator 116. Second clock source 114 is also connected to third clock source 120. Internal clock generator 116 is connected to second clock domain 122. Third clock source 120 is connected to third clock domain 124; [0027])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Ang-Saxena to incorporate the teaching of the limitation indicated above from Pal as indicated above, in order to do effective transition fault testing (Saxena, 3:30).
As per claim 16, Ang-Saxena-Pal teaches The chip testing method applied above in claim 15, Pal teaches further wherein each of the first clock signal, the second clock signal, and the third clock signal is a full-speed clock signal during the chip probe testing. ([0031] FIG. 1, ….. Clock domain 112 is connected to clock generation circuit 126. A second clock source 114 is also connected to clock generation circuit 126 and also to internal clock generator 116. Second clock source 114 is also connected to third clock source 120. Internal clock generator 116 is connected to second clock domain 122. Third clock source 120 is connected to third clock domain 124; [0027])
Claims 3-4, 7-10 are method claims of claims 13-14, 17-20 respectively, they are rejected under the same reason as Claims 13-14 respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsieh et. al, US 20060107137, Chip Testing Methods And Chips
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RONG TANG whose telephone number is (469)295-9106. The examiner can normally be reached Monday - Friday 7:30-5.
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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