Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
2. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitation uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation is: “a zero-core search unit” in claim 10.
Because this claim limitation is being interpreted under 35 U.S.C. 112(f) it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof, i.e., Zero-Core Search Unit 1200 of Figure 1.
If applicant does not intend to have this limitation interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
3. Claim 10-18 are rejected under 35 U.S.C. 112(a) because the claim purports to invoke 35 U.S.C. 112(f) but fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor. Accordingly, the disclosure is not commensurate with the scope of the claim.
4. Claims 10-18 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim element “zero-core search unit” is a means (or step) plus function limitation that invokes 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for the claimed function. The specification and drawings merely show a single box labeled as “zero-core search unit” while restating the functionality present within the claims, without any further description as to the structure within the unit or the algorithm that it implemented to perform the functionality.
Applicant is required to:
(a) Amend the claim so that the claim limitation will no longer be a means (or step) plus function limitation under 35 U.S.C. 112, sixth paragraph; or
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the claimed function without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant is required to clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Surti et al (US 2022/0129521, herein Surti, cited in the IDS dated December 19th, 2025). in view of Higeta (US 2018/0285314).
In the following rejections, the apparatus embodiment of claim 10 will be addressed first.
Regarding claim 10, Surti teaches an apparatus for parallel processing, comprising:
multiple cores that perform parallel processing (Fig 1, [0053], cores of hardware processor);
a zero-core search unit configured to search for a zero core among the multiple cores performing multiplication calculations to process a first instruction, wherein the zero core includes at least one operand of the multiplication calculations performed by each of the multiple core that is zero (Figs 31A-C, [0376-0377], [0380-0386], matrix accelerator logic as zero-core search unit to determine if input to multiplication operation is zero);
a calculation controller configured to perform multiplication calculations in each of the multiple cores and control at least one zero core to perform the multiplication calculations for same operands as operands of a non-zero core, wherein the non-zero core includes operand that is not zero (claim 1, [0380-0385], processing element as calculation controller to perform matrix multiply operations, load or bypass input values if metadata identifies they are zero).
Surti fails to teach the apparatus comprising an error determination unit configured to determine whether calculation error has occurred by comparing a calculation result of the at least one zero core with a calculation result of the non-zero core.
Higeta teaches an apparatus comprising an error determination unit configured to determine whether a calculation error has occurred by comparing a calculation result of at least one zero core with a calculation result of a non-zero core ([0137], [0140], comparing calculation results of zeroth and other cores to detect errors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Surti and Higeta to utilize error detection methods in the multicore processing apparatus. While Surti does disclose the checking of neural network outputs for errors against expected values (Surti [0172]) and for general fault detection in the processing apparatus (Surti [0117]), Surti does not explicitly disclose that outputs of different parallel cores may check for errors during execution. However, as error detection is a routine and conventional aspect of the microprocessor art, analyzing core outputs for errors as disclosed by Higeta would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 11, the combination of Surti and Higeta teaches the apparatus of claim 10, wherein the error determination unit is further configured to determine that there is an error in the multiplication calculations performed by the non-zero core or the zero core when the multiplication calculation result of the at least one zero core does not match the multiplication calculation result of the at least one non-zero core (Higeta [0137], [0140], comparing calculation results to find error).
Regarding claim 12, the combination of Surti and Higeta teaches the apparatus of claim 10, wherein the calculation controller is further configured to control at least three cores, including the non-zero core and the zero core among the multiple cores, to re-perform multiplication calculations for operands calculated by the non-zero core when it is determined that there is an error in the multiplication calculations performed by the non-zero core or the zero core, and wherein the error determination unit is further configured to determine whether there is a fault in the non-zero core or the zero core based on multiplication calculation results of the at least three cores (Higeta Fig 1, three cores, [0135], switch cores and retry operation after error detection, [0137-0140], error determination based on results of cores).
Regarding claim 13, the combination of Surti and Higeta teaches the apparatus of claim 12, wherein the error determination unit is further configured to determine that there is a fault in the non-zero core or the zero core when the multiplication calculation result of the non-zero core or the zero core among the at least three cores does not match calculation results of the other cores (Higeta [0137-0140], error detection by checking core results).
Regarding claim 14, the combination of Surti and Higeta teaches the apparatus of claim 13, wherein the error determination unit is further configured to set, when it is determined that there is a fault in the non-zero core or the zero core, in processing a second instruction, to be processed after the first instruction has been processed, another zero core to perform multiplication calculations to be performed in the non-zero core or zero core determined to have a fault (Higeta [0135], switch cores and retry operation after error detection & instruction control unit used to issue multiple instructions to be processed, [0137-0140], error determination based on results of cores).
Regarding claim 15, the combination of Surti and Higeta teaches the apparatus of claim 12, wherein the calculation controller is further configured to control to re-perform the multiplication calculations without starting processing of a second instruction, to be processed after the first instruction has been processed, when it is determined that there is an error in the multiplication calculations performed by the non-zero core or the zero core (Higeta [0135], switch cores and retry operation after error detection & instruction control unit used to issue multiple instructions to be processed, [0137-0140], error determination based on results of cores).
Regarding claim 16, the combination of Surti and Higeta teaches the apparatus of claim 10, wherein the calculation controller, when it is determined that there is an error in the multiplication calculations performed by the non-zero core or the zero core, and calculation results of two or more zero cores match each other, is further configured to set the multiplication calculation results of the two or more zero cores as the multiplication calculation result of the non-zero core (Higeta [0137-0140], error detection by checking core results).
Regarding claim 17, the combination of Surti and Higeta teaches the apparatus of claim 10, wherein the first instruction includes multiplication calculations for a sparse matrix (Surti [0376-0378], spare matrix multiplication).
Regarding claim 18, the combination of Surti and Higeta teaches the apparatus of claim 10, wherein the zero-core search unit is further configured to search for the zero core by performing logical multiplication calculations for operands to be processed by each of the multiple cores in the first instruction to identify whether at least one operand is zero (Surti [0376-0381], detection of zero inputs of sparse matrix by accelerator logic of systolic array).
Claims 1-9 refer to a method embodiment of the apparatus embodiment of claims 10-18. The above rejections for claims 10-18 are thus applicable to claims 1-9, respectively.
Regarding claim 19, Surti teaches a method of operating an apparatus for parallel processing including multiple cores, comprising:
receiving an instruction that includes N threads as input ([0077], threaded execution);
allocating the N threads to each of multiple cores (Fig 1, [0053], [0062], [0077], allocating threads to cores of processor);
searching for at least one zero thread among the N threads, where at least one of operands of multiplication calculations is zero ([0376-0382], locating zero elements of input operands);
reallocating at least one zero core that has been allocated at least one zero thread to process the same non-zero thread as a non-zero core matched to a non-zero thread that is not the zero thread ([0062], [0129], allocation of threads according to processing requirements and other conditions, [0376-0380], parallel processing of sparse matrices by parallel processing elements of systolic array).
Surti fails to teach determining whether an error has occurred in the multiplication calculations of the non-zero core based on a multiplication calculation result of at least one zero core according to the reallocation and a multiplication calculation result of the non-zero core.
Higeta teaches a method for parallel processing comprising determining whether an error has occurred in the multiplication calculations of a non-zero core based on a multiplication calculation result of at least one zero core according to reallocation and a multiplication calculation result of the non-zero core ([0135], retrying operations after error detection, [0137], [0140], comparing calculation results of zeroth and other cores to detect errors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Surti and Higeta to utilize error detection methods in the multicore processing apparatus. While Surti does disclose the checking of neural network outputs for errors against expected values (Surti [0172]) and for general fault detection in the processing apparatus (Surti [0117]), Surti does not explicitly disclose that outputs of different parallel cores may check for errors during execution. However, as error detection is a routine and conventional aspect of the microprocessor art, analyzing core outputs for errors as disclosed by Higeta would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pillai (US 2022/0206065) discloses a processor for detecting faults in lockstep cores.
Santoni (US 2021/0303372) discloses a processor for comparing outputs of multithreaded processing cores to detect errors.
Anderson (US 2015/0058603) discloses a processor for locating zero operands in a multicore system.
Iacobovici (US 2014/0188965) discloses a processor that restarts execution after an error wherein some operands are zero.
Sinanoglu (US 2013/0332774) discloses a processor for comparing results from identical core operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183