DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 10/29/2024. Claims 1-25 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4, 7, 10, 20, and 25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claims 4, 7, 10, 20, and 25, the specification describes reconstructing missing bits by evaluating syndromes, not by counting mismatches against a "threshold."The closest concept is probabilistic error analysis (e.g., "70% of double error cases can be correctly detected" - col. 21, lines 45-50), but this is not a "threshold quantity" for bitwise parity comparison. Furthermore, there are no examples, algorithms, or descriptions teach selecting or using a "threshold quantity" to recover metadata. Therefore, the specification does not demonstrate possession of an invention that uses threshold-based parity comparison for metadata recovery.
Claims 4, 7, 10, 20 and 25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
As per claims 4, 7, 10, 20, and 25, the specification enables implicit storage/reconstruction via syndrome evaluation with alternative bit values. It does not enable how to: determine the "threshold quantity," whether it's fixed or variable, how it relates to ECC strength, or how to use it for metadata recovery. Therefore, a POSITA would be unable to practice the claimed "threshold quantity" feature without undue experimentation. Thus, the specification lacks enabling guidance for the threshold-based approach
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 7, 10, 20, and 25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term "threshold quantity" in the claims is a relative term which renders the claim indefinite. It is unclear whether the “threshold quantity” is a number, a percentage or a Hamming distance. It is also unclear whether the “threshold quantity” varies with data size, ECC scheme, or error rate and how it is calculated or determined.
The term “threshold quantity” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Therefore, the term, “threshold quantity”, is indefinite because its meaning cannot be ascertained from the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-15 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 8,694,862 B2 ("Saeides").
Claim 13: Saeides discloses a method, comprising:
performing, by a memory device, an error correction code (ECC) decoding operation for a set of data (e.g. col. 20, lines 25-35; Fig. 5B);
determining an error status for the set of data based at least in part on performing the ECC decoding operation (e.g. col. 21, lines 1-5; Fig. 5B outputs); and
recovering metadata information for the set of data, the metadata information previously received by the memory device, based at least in part on the error status for the set of data (col. 20, lines 35-45; col. 21, lines 20-30).
Claim 14: Saeides discloses the method of claim 13, wherein the metadata information is a single metadata bit (e.g. polarity bit - col. 19, lines 1-5 dND multiple-bit metadata (p bits in Fig. 2; col. 20, lines 15-20).
Claim 15: Saeides discloses the method of claim 13, wherein the metadata information comprises multiple metadata bits (e.g. polarity bit - col. 19, lines 1-5 dND multiple-bit metadata (p bits in Fig. 2; col. 20, lines 15-20).
Claim 21: Saeides discloses the method of claim 13, wherein the ECC decoding operation is performed on a first set of parity bits and a second set of parity bits for the set of data, the method further comprising: inverting the first set of parity bits before storing the first set of parity bits in the memory device and based at least in part on the metadata information, wherein the ECC decoding operation is performed after reading the first set of parity bits from the memory device (col. 24, lines 20-30; Fig. 12, XOR 506).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-12 and 16-20, and 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over US 8,694,862 B2 ("Saeides") in view of US 6,457,154 B1 ("Chen").
Claim 1: Saeides teaches a method, comprising:
Metadata bits (e.g., polarity bits, security bits, MRU flags) are implicitly stored within ECC parity bits rather than in separate storage (col. 19, lines 1–10; col. 5, lines 40–50);
the full data value (including metadata) is used to generate check bits;
a reduced data set (without the metadata) is stored (col. 20, lines 15–25; Fig. 5B);
during retrieval, error checking circuitry reconstructs the missing metadata bit by reference to the stored data and stored check bits (col. 20, lines 25–35), wherein the reconstruction may involve performing verification operations with alternative assumed values for the missing bit (col. 21, lines 20–30).
Not explicitly taught by Saeides is performing an error correction code (ECC) decoding operation on a first set of parity bits for a set of data and a second set of parity bits for the set of data; comparing, based at least in part on the ECC decoding operation indicating that the set of data has an uncorrectable error, the first set of parity bits to the second set of parity bits; and recovering metadata information, for the set of data, previously received by the memory device, based at least in part on the comparison.
However, Chen teaches detecting address faults in ECC-protected memory, comprising:
performing ECC decoding using stored check bits and regenerated check bits (col. 4, lines 20–30; col. 5, lines 40–55);
determining whether an error is correctable or uncorrectable (col. 6, lines 10–20).· Generates a second set of parity bits ("extra retrieval parity bits") from the retrieved data and address (col. 22, lines 30–40; Figs. 15–18);
comparing the stored parity bits with the newly generated parity bits via bitwise XOR operations (col. 22, lines 40–45); using the comparison result to distinguish address faults from memory data failures (col. 22, lines 45–55), wherein this comparison is conditioned on the ECC decoding indicating an uncorrectable error (col. 23, lines 1–5).
Therefore, it would have been obvious to a POSITA before the effective filing date of the claimed invention, to implement the teaching of Saeides when the one taught by Chen in order to achieve robust metadata recovery even when ECC indicates errors.
As per claims 18 and 22, the claimed features are rejected similarly to claim 1 above.
Claim 2: Saeides and Chen teach the method of claim 1, further comprising: determining an updated error status for the set of data based at least in part on the comparison. For instance, Chen teaches updating error status based on parity comparison (col. 23, lines 5–10).
As per claim 23, the claimed features are rejected similarly to claim 2 above.
Claim 3: Saeides and Chen teach the method of claim 2, further comprising: determining, based at least in part on the comparison, that the first set of parity bits do not match the second set of parity bits, wherein the metadata information is recovered, and the set of data is determined to be error-free, based at least in part on the determination. For instance, Chen teaches that a parity mismatch can indicate an address fault while data remains error-free (col. 22, lines 45–55).
As per claim 24, the claimed features are rejected similarly to claim 3 above.
Claim 4: Saeides and Chen teach the method of claim 2, but fail to teach that determining, based at least in part on the comparison, that the first set of parity bits comprises a threshold quantity of bits that do not match the second set of parity bits, wherein the metadata information is recovered, and the set of data is determined to have a correctable error, based at least in part on the determination. However, Chen’s syndrome decoding uses thresholds to classify errors (col. 6, lines 10–20; col. 8, lines 15–25). Therefore, the technique of applying threshold logic to parity comparison for metadata recovery would have been obvious to a POSITA, before the effective fling date of the claimed invention.
As per claim 25, the claimed features are rejected similarly to claim 4 above.
Claim 5: Saeides and Chen teach the method of claim 1, wherein comparing the first set of parity bits to the second set of parity bits comprises: performing a bitwise XOR operation on the first set of parity bits and the second set of parity bits. For instance, Chen explicitly uses XOR for parity comparison (col. 22, lines 40–45) and syndrome evaluation (col. 8, lines 15–25).
Claim 6: Saeides and Chen teach the method of claim 5, further comprising: determining a quantity of bits in a set of output bits, from the bitwise XOR operation, that are a first logic value, wherein the metadata information is recovered based at least in part on the quantity of bits. For instance, Chen explicitly uses XOR for parity comparison (col. 22, lines 40–45) and syndrome evaluation (col. 8, lines 15–25).
Claim 7: Saeides and Chen teach the method of claim 6, further comprising: comparing the quantity of bits to a threshold quantity, wherein the metadata information is recovered based at least in part on comparing the quantity of bits to the threshold quantity. For instance, Chen explicitly uses XOR for parity comparison (col. 22, lines 40–45) and syndrome evaluation (col. 8, lines 15–25).
Claim 8: Saeides and Chen teach the method of claim 1, wherein the metadata information is a single metadata bit. For instance, Saeides teaches a single additional bit (e.g., polarity bit) implicitly stored (col. 19, lines 1–5).
Claim 9: Saeides and Chen teach the method of claim 8, further comprising: determining, based at least in part on the comparison, that the first set of parity bits is inverted relative to the second set of parity bits, wherein the metadata information is recovered based at least in part on determining that the first set of parity bits is inverted relative to the second set of parity bits. For instance, Saeides teaches inverting parity based on a polarity bit (col. 24, lines 20–30) and Chen’s comparison technique detects such inversions.
Claim 10: Saeides and Chen teach the method of claim 8, further comprising: determining, based at least in part on the comparison, that the first set of parity bits comprises a threshold quantity of bits that match the second set of parity bits, wherein the metadata information is recovered based at least in part on determining that the first set of parity bits comprises the threshold quantity of bits that match the second set of parity bits. For instance, Saeides teaches inverting parity based on a polarity bit (col. 24, lines 20–30) and Chen’s comparison technique detects such inversions.
Claim 11: Saeides and Chen teach the method of claim 1, further comprising: inverting, based at least in part on the metadata information, the first set of parity bits before storing the first set of parity bits in the memory device; and reading the first set of parity bits from the memory device after storing the first set of parity bits in the memory device, wherein the ECC decoding operation is performed based at least in part on reading the first set of parity bits. For instance, Saeides teaches inverting data/parity based on metadata (col. 24, lines 20–30) and Chen teaches regenerating parity from read data (col. 5, lines 40–55).
Claim 12: Saeides and Chen teach the method of claim 11, further comprising: generating, after reading the set of data, the second set of parity bits based at least in part on the set of data. For instance, Saeides teaches inverting data/parity based on metadata (col. 24, lines 20–30) and Chen teaches regenerating parity from read data (col. 5, lines 40–55).
Claim 16: Saeides teaches the method of claim 13, but fails to teach that the set of data is determined to be error-free, the method further comprising: sending the set of data, along with the metadata information, to a host system. However, Saeides that metadata is recovered from error-free data (col. 21, lines 1-5) and Chen teaches sending corrected data to CPUs (col. 4-5). Therefore, it would have been obvious to a POSITA before the effective filing date of the claimed ivnention, that once metadata is recovered from error-free data (Saeides col. 21, lines 1-5), sending both to a host would have been a standard system operation.
Claim 17: Saeides teaches the method of claim 13, wherein the set of data is determined to have a correctable error, the method further comprising: correcting the set of data based at least in part on the set of data having a correctable error (e.g. col. 21, lines 20-25). Not explicitly taught by Saeides is sending the corrected set of data, along with an indication of the metadata information, to a host system. However, Chen teaches sending corrected data to host (col. 4-5). Therefore, it would have been obvious to a POSITA before the effective filing date of the claimed invention, that once data is corrected, as taught by Saeides, sending both to a host would have been a standard system operation.
Claim 19: Saeides and Chen teach the method of claim 18, further comprising: determining, based at least in part on the comparison, that the first set of parity bits is inverted relative to the second set of parity bits, wherein the metadata information is recovered, and the set of data is determined to be error-free, based at least in part on the first set of parity bits being inverted relative to the second set of parity bits. For instance, Saeides teaches inversion via polarity bit (col. 24, lines 20-30). Chen teaches detecting inversions via XOR comparison (col. 22, lines 40-45).
Claim 20: Saeides and Chen teach the method of claim 18, but fail to teach determining, based at least in part on the comparison, that the first set of parity bits comprises a threshold quantity of bits that match the second set of parity bits, wherein the metadata information is recovered, and the set of data is determined to have a correctable error, based at least in part on the first set of parity bits comprising a threshold quantity of bits that match the second set of parity bits. However, Chen teaches threshold-based syndrome evaluation (col. 8, lines 15-25). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to apply parity matching for metadata recovery.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 1/20/2026