Prosecution Insights
Last updated: July 17, 2026
Application No. 18/930,988

MANUFACTURING METHOD OF CIRCUIT BOARD

Non-Final OA §102
Filed
Oct 29, 2024
Priority
Jan 21, 2021 — provisional 63/139,795 +4 more
Examiner
PATEL, AMOL H
Art Unit
Tech Center
Assignee
Unimicron Technology Corp.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
548 granted / 641 resolved
+25.5% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
15 currently pending
Career history
650
Total Applications
across all art units

Statute-Specific Performance

§103
77.3%
+37.3% vs TC avg
§102
18.8%
-21.2% vs TC avg
§112
1.6%
-38.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 641 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (Pub. No. US 2009/0200682). As to claim 1, Zhang discloses a manufacturing method of a circuit board (fig. 13), the method comprising: providing a first substrate 328, a second substrate 322a, 322b, and a third substrate 330, wherein the third substrate has an opening 318 and comprises a first dielectric layer (see right side of opening 318, a second dielectric layer (see left side of opening 318), and a third dielectric layer (¶0054), the opening penetrates the first dielectric layer and the second dielectric layer, and the opening is fully filled with the third dielectric layer (¶0054); press-fitting the first substrate, the second substrate, and the third substrate so that the second substrate is located between the first substrate and the third substrate (fig. 13); forming a plurality of conductive structures connected to so that the first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path (fig. 13, see 1302 ¶0057, 304, 306); and forming a conductive via structure 312 to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate, wherein the conductive via structure is electrically connected to the first substrate and the third substrate to define a signal path, and the ground path surrounds the signal path (fig. 13). Allowable Subject Matter Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding dependent claim 2, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claim 1, a combination of limitations that discloses wherein providing the first substrate, the second substrate, and the third substrate comprises: providing the first substrate, wherein the first substrate comprises a core layer, a first conductive layer, a first circuit layer, and the first conductive layer and the first circuit layer are respectively disposed on two opposite sides of the core layer; providing the second substrate, wherein the second substrate comprises a base and a plurality of conductive pillars penetrating the base; and providing the third substrate, wherein the third substrate further comprises a second circuit layer, a third circuit layer, a second conductive layer, and a conductive connection layer, the second circuit layer and the third circuit layer are located at two opposite sides of the first dielectric layer, the second dielectric layer covers the third circuit layer and is located between the third circuit layer and the second conductive layer, and the conductive connection layer covers an inner wall of the opening and is connected to the second circuit layer, the third circuit layer, and the second conductive layer. None of the reference art of record discloses or renders obvious such a combination. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wu (Patent No. US 10,448,501) discloses a circuit structure having an outer via and an inner via connecting a plurality of layers.Booth, Jr. et al. (Pub. No. US 2009/0056998) disclosesa multilayer circuit board having an outer and inner via structure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMOL H PATEL whose telephone number is (571)270-7833. The examiner can normally be reached 9:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY THOMPSON can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMOL H PATEL/Examiner, Art Unit 2847
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Prosecution Timeline

Oct 29, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
95%
With Interview (+9.3%)
1y 11m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 641 resolved cases by this examiner. Grant probability derived from career allowance rate.

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