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DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed 10/30/2024 has been fully considered and is attached hereto.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless - (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 9 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Kiso et al (US 2020/0126897).
Regarding Claim 1, Kiso (In Fig 7) discloses an electronic component-incorporating substrate (1C), comprising:
a first substrate (11/21/22/23/24);
a second substrate (15/16/17/18) arranged above the first substrate (11/21/22/23/24), (Fig 7);
a spacer member (15) electrically connecting the first substrate (11/21/22/23/24) and the second substrate (15/16/17/18), (Fig 7); an electronic component (30) mounted on the first substrate (11/21/22/23/24) and disposed between the first substrate (11/21/22/23/24) and the second substrate (15/16/17/18), (Fig 7);
a heat dissipation plate (80, ¶ 81, II. 4-8) disposed between the first substrate (11/21/22/23/24) and the second substrate (15/16/17/18), (Fig 7); and
an encapsulation resin (14, ¶ 36, II. 4-6) filling a gap between the first substrate (11/21/22/23/24) and the second substrate (15/16/17/18) and encapsulating the electronic component (30, Fig 7), wherein
at least both of an upper surface and a lower surface of the heat dissipation plate (80) are embedded in the encapsulation resin (14), (Fig 7),
the heat dissipation plate (80) does not overlap the spacer member (15) in plan view (Fif 7),
the encapsulation resin (14) includes a first outer side surface (outer side surfaces of 14), (Fig 7), and
the heat dissipation plate (80) includes a second outer side surface (outer side surfaces of 80 at outer surfaces of 14) exposed from the first outer side surface (outer side surfaces of 14) of the encapsulation resin (14), (Fig 7).
Regarding Claim 2, Kiso discloses limitations of Claim 1, however Kiso (In Fig 7) further discloses wherein: the heat dissipation plate (80) is disposed between the electronic component (30) and the second substrate (15/16/17/18), (Fig 7); and the encapsulation resin (14) fills a gap between the first substrate (11/21/22/23/24) and the heat dissipation plate (80), a gap between the heat dissipation plate (80) and the second substrate (15/16/17/18), and a gap between the electronic component (30) and the heat dissipation plate (80), (Fig 7).
Regarding Claim 3, Kiso discloses limitations of Claim 1, however Kiso (In Fig 7) further discloses wherein: the heat dissipation plate (80) includes a main body portion (portion of 80 overlapping 30) overlapping the electronic component (30) in plan view (Fig 7), and one or more lead portions (portion of 80 beyond 15 extending to outer side surfaces of 14), (Fig 7) each projecting outward from a side surface of the main body portion (portion of 80 overlapping 30); and each of the one or more lead portions (portion of 80 beyond 15 extending to outer surfaces of 14) includes an outer side surface located at a peripheral edge of the electronic component-incorporating substrate (1C), (Fig 7), the outer side surface of the each of the one or more lead portions (portion of 80 beyond 15 extending to outer side surfaces of 14) corresponding to the second outer side surface (outer side surfaces of 80 at outer surfaces of 14), (Fig 7).
Regarding Claim 4, Kiso discloses limitations of Claim 1, however Kiso (In Fig
7) further discloses wherein: the heat dissipation plate (80) includes a main body portion (portion of 80 overlapping 30) overlapping the electronic component (30) in plan view (Fig 7), and lead portions (portion of 80 beyond 15 extending to outer side surfaces of 14) each projecting outward from a side surface of the main body portion (portion of 80 overlapping 30), (Fig 7); and the spacer member (15) is one of spacer members (15/15) that are disposed between the lead portions (portion of 80 beyond 15 extending to outer side surfaces of 14) to surround a peripheral edge of the main body portion (portion of 80 overlapping 30) in plan view (Fig 7).
Regarding Claim 5, Kiso discloses limitations of Claim 4, however Kiso (In Fig
7) further discloses wherein: the encapsulation resin (14) fills a gap between the lead portions (portion of 80 beyond 15 extending to outer side surfaces of 14) and a gap between the spacer members (15), (Fig 7).
Regarding Claim 9, Kiso discloses limitations of Claim 1, however Kiso (In Fig
7) further discloses wherein the second outer side surface (outer side surfaces of 80 at outer surfaces of 14) is flush with the first outer side surface (outer side surfaces of 14), (Fig 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. § 103 as being unpatentable over Kiso in view of Li et al (US 2024/0266245).
Regarding Claim 6, Kiso discloses limitations of Claim 3, however Kiso does not disclose wherein the main body portion includes a recess that is recessed upward from a lower surface of the main body portion, and the recess overlaps the electronic component in plan view.
Instead, Li (In Fig 2A) teaches wherein the main body portion (portion of 300a overlapping 120a) includes a recess (recess in 300a accommodating 120a) that is recessed upward from a lower surface (lower surface of 300b) of the main body portion (portion of 300a overlapping 120a), and the recess (recess in 300a accommodating 120a) overlaps the electronic component (120a) in plan view (Fig 2A).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Kiso with Li with the main body portion including a recess that is recessed upward from a lower surface of the main body portion and the recess overlapping the electronic component in plan view to benefit from ensuring continuous and reliable operation of the chip by reducing the thermal resistance of the chip to optimize the heat dissipation thereof (Li ¶ 3, II. 9-17).
Claim 7 is rejected under 35 U.S.C. § 103 as being unpatentable over Kiso in view of Nakamura et al (US 5,581,443).
Regarding Claim 7, Kiso discloses limitations of Claim 3, however Kiso does not disclose wherein the main body portion is larger in size than the electronic component in plan view, the main body portion includes an opening extending through the main body portion in a thickness-wise direction, and the opening overlaps the electronic component in plan view.
Instead, Nakamura (In Fig 3) teaches wherein the main body portion (portion of 67 overlapping 23, Col 10, II. 40-43) is larger in size than the electronic component (23) in plan view (Fig 3), the main body portion (portion of 67 overlapping 23) includes an opening (75) extending through the main body portion (portion of 67 overlapping 23) in a thickness-wise direction (Fig 3), and the opening (75) overlaps the electronic component (23) in plan view (Fig 3).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Kiso with Nakamura with the main body portion being larger in size than the electronic component in plan view and the main body portion including an opening extending through the main body portion in a thickness-wise direction and the opening overlapping the electronic component in plan view to benefit from efficiently dissipating heat from IC chip outwards without transmitting the heat to the circuit board (Nakamura Col 2, II. 42-51).
Claim 8 is rejected under 35 U.S.C. § 103 as being unpatentable over Kiso in view of Nakamura and further in view of Ota (JP2013211480).
For the purpose of citation, Examiner used machine translation of JP2013211480, said translation has been provided herewith to the Applicant.
Regarding Claim 8, Kiso in view of Nakamura discloses limitations of Claim 7, however Kiso as modified does not disclose wherein the electronic component is disposed inside the opening of the heat dissipation plate.
Instead, Ota (In Fig 13d) teaches wherein the electronic component (90) is disposed inside the opening of the heat dissipation plate (22a, ¶ 20, II. 4-5).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Kiso with Nakamura and further with Ota with the electronic component being disposed inside the opening of the heat dissipation plate to benefit from dissipating heat from electronic component (Ota ¶ 20, II. 4-5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; Chip Embedded Substrate and Method of Producing the Same US 2011/0256662, Semiconductor Apparatus and Method of Making Semiconductor Apparatus US 2022/0399293, Embedded Printed Circuit Board US 2023/0276575, Package, Semiconductor Device and Method for Fabricating the Semiconductor Device US 6,555,900. Other pertinent art made of record are on form PTO-892 notice of reference cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIR JALALI whose telephone number is (303)297-4308. The examiner can normally be reached on Monday - Friday 8:30am - 5:00pm, Mountain Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached on 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMIR A JALALI/Primary Examiner, Art Unit 2841
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