DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-9 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/17/2024 has been considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to JP2023-189226 for 11/06/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
BIFURCATED METAL-INSULATOR-METAL CAPACITOR LAYOUT
Claim Objections
Claims 2-4 are objected to because of the following informalities:
Examiner recommends that claims 2-4 are amended in order to increase clarity of the claimed subject matter and to simplify the language of the claims.
Regarding claim 2, examiner suggests amendment of the claim to read “The semiconductor device according to claim 1, wherein the MIM capacitor does not overlap the gate electrode of the transistor.”
Regarding claim 3, examiner suggests amendment of the claim to read “The semiconductor device according to claim 1, wherein the MIM capacitor does not extend beyond the area of the first electrode when viewed in a direction perpendicular to the surface.”
Regarding claim 4, examiner suggests amendment of the claim to read “The semiconductor device according to claim 1, wherein the MIM capacitor includes a first portion that does not extend beyond the area of the first electrode when viewed in a direction perpendicular to the main surface…”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fisher et al. (US PGPub 2024/0105712) in view of Oh et al. (US PGPub 2007/0145452).
Regarding claim 1, Fisher teaches (Figs. 3a-3c, Fig. 3c) a semiconductor device comprising: a transistor (10, [0073]) provided on a main surface (top) of a substrate (190, [0081]) having the main surface, and including a first electrode (305, [0073]) including an ohmic electrode ([0082]); a MIM capacitor (330, [0081]) formed above the transistor and including a second electrode (331, [0081]) a first electrically insulating layer (333, [0082]) provided on the second electrode, and a third electrode (332, [0081]) provided on the first electrically insulating layer; but does not explicitly teach: a second electrically insulating layer provided between the first electrode and the second electrode; and a plurality of vias penetrating the second electrically insulating layer and electrically connecting the first electrode and the second electrode to each other.
In analogous art, Oh teaches (Fig. 10) a second electrically insulating layer (123, [0033]) provided between the first electrode (113a, [0033]) and the second electrode (127, [0033]); and a plurality of vias (121, 117, [0033]) penetrating the second electrically insulating layer and electrically connecting the first electrode and the second electrode to each other ([0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Fisher and of Oh to include a second electrically insulating layer provided between the first electrode and the second electrode; and a plurality of vias penetrating the second electrically insulating layer and electrically connecting the first electrode and the second electrode to each other in order to reduce parasitic capacitance between the MIM capacitor and the lower electrode by increasing the distance between the capacitor and the electrode (Oh, [0007]).
Regarding claim 2, Fisher in view of Oh teaches (Fisher, Figs. 3A-3C, annotated Fig. 3C below) the semiconductor device according to claim 1, wherein the MIM capacitor (330, [0081]) is provided to avoid an area above a gate electrode (310, [0073]) of the transistor (10, [0073]). As shown in the annotated Fig. 3c below, the MIM capacitor is fully outside of an area, GEa, directly overlying the gate electrode, 310.
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Regarding claim 3, Fisher in view of Oh teaches (Fisher, Figs. 3A-3C, Fig. 3A) the semiconductor device according to claim 1, wherein the MIM capacitor (330, [0081]) fits in an area above the first electrode (305, [0073]) when viewed in a direction perpendicular to the main surface. The MIM capacitor can be seen to be fully inside an outline of the first electrode in a plan view.
Regarding claim 4, Fisher in view of Oh teaches (Fisher, Figs. 3A-3C, Fig. 3A) the semiconductor device according to claim 1, wherein the MIM capacitor (330', [0081]) includes a first portion (330', [0081]) fitting in an area above the first electrode (305, [0073]) when viewed in a direction perpendicular to the main surface, and a second portion (330x, [0094]) provided outside the transistor (10, [0073]) when viewed in the direction perpendicular to the main surface, the second portion being continuous with the first portion ([0094]).
Regarding claim 5, Fisher in view of Oh teaches (Fisher, Figs. 3A-3C) the semiconductor device according to claim 1, wherein the transistor (10, [0131]) is a HEMT including a III-V group semiconductor ([0131]).
Regarding claim 6, Fisher in view of Oh teaches the semiconductor device according to claim 1, wherein a dielectric constant of the first electrically insulating layer (Fisher, 333, [0083]) is larger than a dielectric constant of the second electrically insulating layer (Oh, 123, [0012]). Fisher teaches use of high-k dielectric materials, such as TiO2, which has a higher dielectric constant than the low-k dielectric materials, such as fluorosilicate glass, as taught by Oh ([0043]).
Regarding claim 7, Fisher in view of Oh teaches (Oh, Fig. 10) the semiconductor device according to claim 1, wherein a thickness of the first electrically insulating layer (131, [0034]) in a direction perpendicular to the main surface is smaller than a thickness of the second electrically insulating layer (123, [0043]) in the direction perpendicular to the main surface. See Figure.
Regarding claim 8, Fisher in view of Oh teaches (Fisher, Figs. 3A-3C, Fig. 3A) the semiconductor device according to claim 1, wherein a thickness of the second electrode (331, [0081]) in a direction perpendicular to the main surface is smaller than a thickness of the first electrode (305, [0073]) in the direction perpendicular to the main surface. The second electrode is seen, in the plan view, to be less wide than the first electrode.
Regarding claim 9, Fisher in view of Oh teaches (Oh, Fig. 10) the semiconductor device according to claim 1, wherein lengths of the plurality of vias (117, 121, [0043]) in a direction perpendicular to the main surface is 0.1 μm to 10 μm (Oh, [0043]). The vias span the thickness of the insulating layer, which has a thickness up to 2μm.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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