DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 2, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 14-17 and 20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yun et al (U.S. Patent Pub. No. 2022/0199034; already of record) in view of Heo et al (U.S. Patent Pub. No. 2023/0073923; already of record) and in view of Choi et al (U.S. Patent Pub. No. 2023/0215378; already of record).
Regarding claim 1, Yun discloses a gate driver (128) including a plurality of stages (ST(1)-ST(k)), (fig. 4, [0090]), each of the plurality of stages comprising:
a common circuit (602, 604, 606, 608, 610, 612 and 616) which controls a voltage of a first control node (Q1), a voltage of a second control node (Q2), and a voltage of an inverted control node (QB), (fig. 4, [0188, 0220 and 0241]); and
an individual circuit (614) which outputs a plurality of scan signals (SCOUT(n) and SCOUT(n+1)) in response to the voltage of the first control node (Q1) and the voltage of the inverted control node (QB), (fig. 8, [0231]),
wherein the individual circuit (614) includes:
a plurality of scan buffer transistors (T71 and T73) which output a plurality of scan clock signals (SCCLK(n) and SCCLK(n+1)) as the plurality of scan signals SCOUT(n) and SCOUT(n+1) in response to the voltage of the first control node (Q1), (fig. 8, [0233-0235 and 0237-0239]); and
a scan hold transistor (T72 and T74) which maintains the plurality of scan signals (SCOUT(n) and SCOUT(n+1)) at a first low voltage (GVSS1) in response to the voltage of the inverted control node (QB), (fig. 8, [0236 and 0240]).
However, Yun does not mention the scan hold transistor include a second electrode connected to a plurality of scan output nodes including a first scan output node, a second scan output node, a third scan output node, and a fourth scan output node.
However, Yun does not mention a single scan hold transistor.
In a similar field of endeavor, Heo teaches a gate driver (120L) comprising:
a plurality of scan buffer transistors (TR1-1a and TR1-1b); and
a single scan hold transistor (TR1-2) which maintains the plurality of scan signals (i.e. when signal EM OUT outputs during periods 1 and 3) at a first low voltage (GVSS) in response to the voltage of the inverted control node (QB1),
wherein the single scan hold transistor (TR1-2) includes a gate electrode connected to the inverted control node (QB1), a first electrode which receives the first low voltage (GVSS), and a second electrode connected to a plurality of scan output nodes including a first scan output node (i.e. output node of transistor TR1-1a) and a second scan output node (i.e. output node of transistor TR1-1b), (fig. 13a-13b, [0173-0175 and 0179-0181]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yun, by specifically providing the single scan hold transistor, as taught by Heo, for the purpose of stably maintaining an output waveform, [0009].
However, Yun in view of Heo does not mention a third scan output node and a fourth scan output node.
In a similar field of endeavor, Choi teaches a scan hold transistors (T72, T74, T76 and T78) which maintains the plurality of scan signals at a first low voltage (GVSS1) in response to the voltage of the inverted control node (QB), wherein the scan hold transistor includes a gate electrode connected to the inverted control node (QB), a first electrode which receives the first low voltage (GVSS1), and a second electrode connected to a plurality of scan output nodes (NO2, NO3, NO4 and NO5) including a first scan output node (NO2), a second scan output node (NO3), a third scan output node (NO4), and a fourth scan output node (NO5), (fig. 5, [0178]). Hence, applying the concept of Heo who teaches the single scan hold transistor (TR1-2) into Choi’s teaching of having the first through fourth scan output nodes (NO2-NO5) would result in the signal scan hold transistor (TR1-2) includes a gate electrode connected to the inverted control node (QB1), a first electrode which receives the first low voltage (GVSS), and a second electrode connected to a plurality of scan output nodes (NO2-NO5 of Choi) including a first scan output node (NO2), a second scan output node (NO3), a third scan output node (NO4) and a fourth scan output node (NO5).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yun in view of Heo, by specifically providing the first to fourth scan output nodes, as taught by Choi, for the purpose of increasing the display area and decreasing the size of the gate driving circuit, [0006].
Regarding claim 2, Choi discloses wherein the plurality of scan buffer transistors (T71, T73, T75 and T77) include:
a first scan buffer transistor (T71) including a gate electrode connected to the first control node (Q), a first electrode which receives a first scan clock signal (SCCLK(i)), and a second electrode connected to the first scan output node (NO2) which outputs a first scan signal (SCOUT(i));
a second scan buffer transistor (T73) including a gate electrode connected to the first control node (Q), a first electrode which receives a second scan clock signal (SCCLK(i+1)), and a second electrode connected to the second scan output node (NO3) which outputs a second scan signal (SCOUT(i+1));
a third scan buffer transistor (T73) including a gate electrode connected to the first control node (Q), a first electrode which receives a third scan clock signal (SCCLK(i+2)), and a second electrode connected to the third scan output node (NO4) which outputs a third scan signal (SCOUT(i+2)); and
a fourth scan buffer transistor (T77) including a gate electrode connected to the first control node (Q), a first electrode which receives a fourth scan clock signal (SCCLK(i+3)), and a second electrode connected to the fourth scan output node (NO5) which outputs a fourth scan signal (SCOUT(i+3)), (fig. 5, [0176]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yun in view of Heo, by specifically providing the first to fourth clock signals, as taught by Choi, for the purpose of increasing the display area and decreasing the size of the gate driving circuit, [0006].
Regarding claim 3, Choi discloses wherein, in a first period (P1-P8) in which a voltage having a turn-on voltage level is applied to the first control node (i.e. when node Q has a high voltage level), first to fourth pulses corresponding to the first to fourth scan clock signals (SCCLK(i) – SCCLK(i+3)), respectively, are sequentially output from the first to fourth scan output nodes, respectively, (fig. 12, [0235-0238]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yun in view of Heo, by specifically providing the first to fourth scan clock signals, as taught by Choi, for the purpose of increasing the display area and decreasing the size of the gate driving circuit, [0006].
Regarding claim 4, Choi discloses wherein, in a second period (period after P8) in which a voltage having a turn-on voltage level (GVDD2) is applied to the inverted control node (QB), the first low voltage (GVSS1) is output from the first to fourth output nodes (i.e. nodes NO2-NO5 outputting signals SCOUT(i)-SCOUT(i+3) at low voltage GVSS1), (fig. 12, [0241]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yun in view of Heo, by specifically providing the first to fourth scan signals, as taught by Choi, for the purpose of increasing the display area and decreasing the size of the gate driving circuit, [0006].
Regarding claim 7, Yun discloses wherein the common circuit (602, 604, 606, 608, 610, 612 and 616) includes:
a carry buffer transistor (T81) which outputs a carry clock signal (CRCLK(k)) as a carry signal (C(k)) in response to the voltage of the second control node (Q2); and
a carry hold transistor (T82) which maintains the carry signal (C(k)) at a second low voltage (GVSS4) in response to the voltage of the inverted control node (QB), (fig. 8, [0155-0159]).
Regarding claim 14, Yun in view of Heo and in view of Choi discloses everything as mentioned above in claim 1. In addition, Yun discloses a display device (fig. 1, [0060]), comprising:
a display panel (106) including a plurality of pixels (SP), (fig. 2, [0061]);
a data driver (126) which provides a plurality of data signals (data lines 14 for outputting data voltages) to the display panel (106), (fig. 1, [0062-0063]); and
a gate driver (128) including a plurality of stages (ST(1)-ST(k)) which provide a plurality of scan signals (SCOUT(1)-SCOUT(n)) to the display panel (106), (fig. 4, [0102-0103]).
Regarding claim 15, please refer to claim 2 for details.
Regarding claim 16, Yun discloses wherein each of the plurality of pixels (SP) includes:
a first pixel transistor (DT) including a gate electrode connected to a first pixel node (N1), a first electrode which receives a first power voltage (EVDD), and a second electrode connected to a second pixel node (N2), (fig. 3, [0076]);
a second pixel transistor (ST1) including a gate electrode which receives a scan signal (SCAN) of the plurality of scan signals, a first electrode which receives a data signal (Vdata) of the plurality of data signals, and a second electrode connected to the first pixel node (N1), (fig. 3, [0078-0079]);
a third pixel transistor (ST2) including a gate electrode, a first electrode which receives an initialization voltage (Vpre) (i.e. receives Vpre when switch SW1 is ON), and a second electrode connected to the second pixel node (N2), (fig. 3, [0080-0082]);
a storage capacitor (Cst) including a first electrode connected to the first pixel node (N1) and a second electrode connected to the second pixel node (N2), (fig. 3, [0077]); and
a light emitting element (OLED) including a first electrode connected to the second pixel node (N2) and a second electrode which receives a second power voltage (EVSS), (fig. 3, [0075]).
Regarding claim 17, Yun discloses wherein the gate electrode of the third pixel transistor (ST2) receives the scan signal (SEN), (fig. 3, [0080-0081]).
Regarding claim 20, please refer to claim 7 for details.
Claim(s) 5 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Heo in view of Choi and in view of Park et al (U.S. Patent Pub. No. 2020/0380911; already of record).
Regarding claim 5, Yun in view of Heo and in view of Choi discloses everything as specified above in claim 1. However, Yun in view of Heo and in view of Choi does not mention a plurality of sensing buffer transistors.
In a similar field of endeavor, Park teaches wherein the individual circuit (150a and 150b) further includes:
a plurality of sensing buffer transistors (T20 and T29) which output a plurality of sensing clock signals (CLK3_SS and CLK4_SS) as a plurality of sensing signals (SS(i) and SS(i+1)) in response to the voltage of the first control node (QN1); and
a sensing hold transistor (T21 and T30) which maintains the plurality of sensing signals (SS(i) and SS(i+1)) at the first low voltage (VGL2) in response to the voltage of the inverted control node (QN2), (fig. 4, [0084, 0127-0128 and 0133-0134]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yun in view of Heo and in view of Choi, by specifically providing the sensing buffer transistors, as taught by Park, for the purpose of having output buffers configured to share one drive controller, [0006].
Regarding claim 18, please refer to claim 5 for details.
Regarding claim 19, Park discloses wherein the gate electrode of the third pixel transistor (M3) receives a sensing signal (SSi) of the plurality of sensing signals (SS(i) and SS(i+1)), (fig. 2, [0055]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Yun in view of Heo and in view of Choi, by specifically providing the third pixel transistor receiving the sensing signal, as taught by Park, for the purpose of measuring current flowing through the LED, [0055].
Allowable Subject Matter
Claims 6 and 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of amendment, the reference of Choi has been added for new grounds of rejection.
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/LONG D PHAM/Primary Examiner, Art Unit 2623
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