Email Communication
Applicant is encouraged to authorize the Examiner to communicate via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502, 502.03.
DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements filed 10/30/2024 has been fully considered and is attached hereto.
Specification
The disclosure is objected to because of the following informalities: reference character “252” has been used in drawings (Fig. 5), however specification does not mention it. Correction is required. See MPEP § 608.01(b).
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “252” has been used in drawings (Fig. 5), however specification does not mention it.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the Claims. Therefore, the “a fourth insulation layer on the lower surface of the semiconductor substrate and surrounding the TSV and the thermal head” in Claim 14 must be shown or the feature canceled from the Claim. No new matter should be entered.
Drawing (Fig 13) illustrates fourth insulation layer 240 surrounding thermal seed layer 232 and thermal head 212, however fourth insulation layer 240 does not surround the TSV 120.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended”. If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 15 is objected to because of the following claim construction informalities:
● In Claim 15, Line 6, “TSV” should be changed to read - - TSV, - -.
● In Claim 15, Line 15, “head portion” should be changed to read - - head portion, - -.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 1, 3-4, 6, 8 and 13-15 of Choi et al (17/696,989).
Although the claims at issue are not identical, they are not patentably distinct from each other.
With respect to Claim 1, Claim 1 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), A thermal pad of a semiconductor chip, the thermal pad comprising (verbatim): a thermal core in a trench at a lower surface of a semiconductor substrate (verbatim), the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate (verbatim); a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate (verbatim), the thermal head being configured to dissipate the heat in the thermal core (verbatim); a first insulation layer between an inner surface of the trench and the thermal core (verbatim); a second insulation layer between the first insulation layer and the thermal core (verbatim); and a seed layer interposed between the thermal core and the thermal head (verbatim), the seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head (the seed layer surrounding a side surface and a lower surface of the thermal head and exposing only an upper surface of the thermal head).
With respect to Claim 2, Claim 1 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the first insulation layer and the second insulation layer each extend to the lower surface of the semiconductor substrate (a first insulation layer extending onto the lower surface of the semiconductor substrate; a second insulation extending onto the lower surface of the semiconductor substrate).
With respect to Claim 3, Claim 3 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the first insulation layer includes an oxide (verbatim).
With respect to Claim 4, Claim 4 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the second insulation layer includes silicon nitride (verbatim).
With respect to Claim 5, Claim 1 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), a third insulation layer between the second insulation layer and the thermal core (a third insulation layer entirely within the trench between the second insulation layer and the thermal core).
With respect to Claim 6, Claim 6 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the second insulation layer includes silicon nitride (verbatim).
With respect to Claim 7, Claim 1 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the third insulation layer is entirely within the trench (verbatim).
With respect to Claim 8, Claim 8 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), A semiconductor chip comprising (verbatim): a semiconductor substrate including a trench at a lower surface thereof (verbatim); a through silicon via (TSV) vertically extending through the semiconductor substrate (verbatim); a thermal core in the trench (verbatim), the thermal core being configured to receive heat generated from the TSV (verbatim); a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate (verbatim), the thermal head being configured to dissipate the heat in the thermal core (verbatim); a first insulation layer between an inner surface of the trench and the thermal core (verbatim); a second insulation layer between the first insulation layer and the thermal core (verbatim); and a seed layer interposed between the thermal core and the thermal head (verbatim), the seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head (the seed layer surrounding a side surface and a lower surface of the thermal head and exposing only an upper surface of the thermal head).
With respect to Claim 9, Claim 8 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the first insulation layer and the second insulation layer each extend to the lower surface of the semiconductor substrate (a first insulation layer extending onto the lower surface of the semiconductor substrate; a second insulation extending onto the lower surface of the semiconductor substrate).
With respect to Claim 10, Claim 8 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), a third insulation layer between the second insulation layer and the thermal core (a third insulation layer entirely within the trench between the second insulation layer and the thermal core).
With respect to Claim 11, Claim 8 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the third insulation layer is entirely within the trench (a third insulation layer entirely within the trench between the second insulation layer and the thermal core).
With respect to Claim 12, Claim 13 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses) a head portion protruding from the lower surface of the semiconductor substrate on the TSV (verbatim).
With respect to Claim 13, Claim 14 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses) a seed layer between the TSV and the head portion (verbatim).
With respect to Claim 14, Claim 15 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses) a fourth insulation layer on the lower surface of the semiconductor substrate and surrounding the TSV and the thermal head (verbatim).
With respect to Claim 15, Claim 8, 13 and 14 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses) A semiconductor chip comprising (Cl. 8, verbatim): a semiconductor substrate including a trench at a lower surface thereof (Cl. 8, verbatim); a through silicon via (TSV) vertically extending through the semiconductor substrate (Cl. 8, verbatim); a head portion protruding from the lower surface of the semiconductor substrate on the TSV (Cl. 13, verbatim ) a thermal core in the trench (Cl. 8, verbatim), the thermal core being configured to receive heat generated from the TSV (Cl. 8, verbatim); a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate (Cl. 8, verbatim), the thermal head being configured to dissipate the heat in the thermal core (Cl. 8, verbatim); a first insulation layer between an inner surface of the trench and the thermal core (Cl. 8, verbatim); a second insulation layer between the first insulation layer and the thermal core (Cl. 8, verbatim); and a first seed layer between the TSV and the head portion (Cl. 14, verbatim) a second seed layer interposed between the thermal core and the thermal head (Cl. 8, a seed layer interposed between the thermal core and the thermal head), the second seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head (Cl. 8, the seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head).
With respect to Claim 16, Claim 8 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the first insulation layer and the second insulation layer each extend to the lower surface of the semiconductor substrate (a first insulation layer extending onto the lower surface of the semiconductor substrate; a second insulation extending onto the lower surface of the semiconductor substrate).
With respect to Claim 17, Claim 8 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), a third insulation layer between the second insulation layer and the thermal core (a third insulation layer entirely within the trench between the second insulation layer and the thermal core).
With respect to Claim 18, Claim 8 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the third insulation layer is entirely within the trench (verbatim).
With respect to Claim 19, Claim 3 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the first insulation layer includes an oxide (verbatim).
With respect to Claim 20, Claim 4 of the ‘989 reference recites (recitation of the ‘989 reference in parentheses), wherein the second insulation layer includes silicon nitride (verbatim).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-9, 15-16 and 19 are rejected under 35 U.S.C. § 103 as being unpatentable over Gambino et al (US 2016/0181174) Figs 1A-3A in view of Fig 1 and further in view of Sukumaran et al (US 9,805,977).
Regarding Claim 1, Gambino (In Figs 1A-3A) discloses a thermal pad (134A), (Fig 1A) of a semiconductor chip (116), (Fig 3A) , the thermal pad (134A) comprising:
a thermal core (138) in a trench (131), at a lower surface of a semiconductor substrate (310), (Fig 3A), the thermal core (138) being configured to receive heat (heat thru 140) generated from a through silicon via (TSV) (122) vertically extending through the semiconductor substrate (310), (Fig 1A);
a first insulation layer (146) between an inner surface of the trench (131) and the thermal core (138), (Fig 3A); a second insulation layer (140) between the first insulation layer (146) and the thermal core (138), (Fig 3A).
However, Gambino Figs 1A-3A does not disclose wherein a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core.
Instead, Gambino (In Fig 1) teaches wherein a thermal head (104/106) connected to the thermal core (108) and protruding from the lower surface of the semiconductor substrate (310), the thermal head (104/106) being configured to dissipate the heat in the thermal core (108), (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 with a thermal head being connected to the thermal core and protruding from the lower surface of the semiconductor substrate to benefit from reduced operating temperature, increased reliability with higher performance (Gambino, ¶ 4, II. 1-7), however Gambino as modified does not disclose wherein a seed layer interposed between the thermal core and the thermal head, the seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head.
Instead, Sukumaran (In Fig 13) teaches wherein a seed layer (162) interposed between the thermal core (118) and the thermal head (168), the seed layer (162) surrounding a side surface and a lower surface of the thermal head (168) and exposing an upper surface of the thermal head (168), (Fig 13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 and further with Sukumaran with a seed layer being interposed between the thermal core and the thermal head and surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head to benefit from providing a more robust interconnection to the TSV while preventing unwanted breakage or damage that may be conventionally caused by the back side grind, thereby increasing the interconnect yield in the wafer (Sukumaran, Col 3, II. 20-25).
Regarding Claim 2, Gambino Figs 1A-3A in view of Fig 1 and further in view of Sukumaran discloses the limitations of Claim 1, however Gambino (In Figs 1A-3A) further discloses wherein the first insulation layer (146) and the second insulation layer (140) each extend to the lower surface of the semiconductor substrate (310), (Fig 3A).
Regarding Claim 3, Gambino Figs 1A-3A in view of Fig 1 and further in view of Sukumaran discloses the limitations of Claim 1, however Gambino (In Figs 1A-3A) further discloses wherein the first insulation layer (146) includes an oxide (¶ 44, 1-5).
Regarding Claim 8, Gambino (In Figs 1A-3A) discloses a semiconductor chip (116), (Fig 3A) comprising: a semiconductor substrate (310) including a trench (131) at a lower surface thereof (Fig 3A); a through silicon via (TSV) (122) vertically extending through the semiconductor substrate (310), (Fig 1A); a thermal core (138) in the trench (131), the thermal core (138) being configured to receive heat (heat thru 140) generated from the TSV (122), (Fig 1A); a first insulation layer (146) between an inner surface of the trench (131) and the thermal core (138), (Fig 3A); a second insulation layer (140) between the first insulation layer (146) and the thermal core (138), (Fig 3A).
However, Gambino Figs 1A-3A does not disclose wherein a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core
Instead, Gambino (In Fig 1) teaches wherein a thermal head (104/106) connected to the thermal core (108) and protruding from the lower surface of the semiconductor substrate (310), the thermal head (104/106) being configured to dissipate the heat in the thermal core (108), (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 with a thermal head being connected to the thermal core and protruding from the lower surface of the semiconductor substrate and being configured to dissipate the heat in the thermal core to benefit from reduced operating temperature, increased reliability with higher performance (Gambino, ¶ 4, II. 1-7), however Gambino as modified does not disclose wherein a seed layer interposed between the thermal core and the thermal head, the seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head.
Instead, Sukumaran (In Fig 13) teaches wherein a seed layer (162) interposed between the thermal core (118) and the thermal head (168), the seed layer (162) surrounding a side surface and a lower surface of the thermal head (168) and exposing an upper surface of the thermal head (168), (Fig 13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 and further with Sukumaran with a seed layer being interposed between the thermal core and the thermal head and surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head to benefit from providing a more robust interconnection to the TSV while preventing unwanted breakage or damage that may be conventionally caused by the back side grind, thereby increasing the interconnect yield in the wafer (Sukumaran, Col 3, II. 20-25).
Regarding Claim 9, Gambino Figs 1A-3A in view of Fig 1 and further in view of Sukumaran discloses the limitations of Claim 8, however Gambino (In Figs 1A-3A) further discloses wherein the first insulation layer (146) and the second insulation layer (140) each extend to the lower surface of the semiconductor substrate (310), (Fig 3A).
Regarding Claim 15, Gambino (In Figs 1A-3A) discloses a semiconductor chip (116), (Fig 3A) comprising:
a semiconductor substrate (310) including a trench (131) at a lower surface thereof (Fig 3A);
a through silicon via (TSV) (122) vertically extending through the semiconductor substrate (310), (Fig 3A);
a head portion (110, 124) protruding from the lower surface of the semiconductor substrate (310) on the TSV (122), (Fig 3A)
a thermal core (138) in the trench (131), the thermal core (138) being configured to receive heat generated from the TSV (122), (Fig 3A);
a first insulation layer (146) between an inner surface of the trench (131) and the thermal core (138), (Fig 3A);
a second insulation layer (140) between the first insulation layer (146) and the thermal core (138), (Fig 3A); However, Gambino Figs 1A-3A does not disclose wherein a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core
Instead, Gambino (In Fig 1) teaches wherein a thermal head (104/106) connected to the thermal core (108) and protruding from the lower surface of the semiconductor substrate (310), the thermal head (104/106) being configured to dissipate the heat in the thermal core (108), (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 with a thermal head being connected to the thermal core and protruding from the lower surface of the semiconductor substrate and being configured to dissipate the heat in the thermal core to benefit from reduced operating temperature, increased reliability with higher performance (Gambino, ¶ 4, II. 1-7), however Gambino as modified does not disclose wherein a first seed layer between the TSV and the head portion a second seed layer interposed between the thermal core and the thermal head, the second seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head.
Instead, Sukumaran (In Fig 13) teaches wherein a first seed layer (162) between the TSV (112) and the head portion (168) a second seed layer (162) interposed between the thermal core (150) and the thermal head (168), (Fig 13), the second seed layer (162) surrounding a side surface and a lower surface of the thermal head (168) and exposing an upper surface of the thermal head (168), (Fig 13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 and further with Sukumaran with a first seed layer between the TSV and the head portion a second seed layer interposed between the thermal core and the thermal head, the second seed layer surrounding a side surface and a lower surface of the thermal head and exposing an upper surface of the thermal head to benefit from providing a more robust interconnection to the TSV while preventing unwanted breakage or damage that may be conventionally caused by the back side grind, thereby increasing the interconnect yield in the wafer (Sukumaran, Col 3, II. 20-25).
Regarding Claim 16, Gambino Figs 1A-3A in view of Fig 1 and further in view of Sukumaran discloses the limitations of Claim 15, however Gambino (In Figs 1A-3A) further discloses wherein the first insulation layer (146) and the second insulation layer (140) each extend to the lower surface of the semiconductor substrate (310), (Fig 3A).
Regarding Claim 19, Gambino Figs 1A-3A in view of Fig 1 and further in view of Sukumaran discloses the limitations of Claim 15, however Gambino (In Figs 1A-3A) further discloses wherein the first insulation layer (146) includes an oxide (¶ 44, 1-5).
Claims 4 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over Gambino Figs 1A-3A in view of Fig 1 further in view of Sukumaran and further in view of Chen et al (US 2011/0244676).
Regarding Claim 4, Gambino Figs 1A-3A in view of Gambino Fig 1 and further in view of Sukumaran discloses the limitations of Claim 1, however Gambino as modified does not disclose wherein the second insulation layer includes silicon nitride.
Instead, Chen (In Fig 9) teaches wherein the second insulation layer (32) includes silicon nitride (¶ 28, II. 1-7).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further in view of Sukumaran and further with Chen with the second insulation layer including silicon nitride to benefit from providing a diffusion barrier preventing metal diffusion, while providing adhesion between metal and dielectric (Chen, ¶ 28, II. 1-7).
Regarding Claim 20, Gambino Figs 1A-3A in view of Gambino Fig 1 and further in view of Sukumaran discloses the limitations of Claim 15, however Gambino as modified does not disclose wherein the second insulation layer includes silicon nitride.
Instead, Chen (In Fig 9) teaches wherein the second insulation layer (32) includes silicon nitride (¶ 28, II. 1-7).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further in view of Sukumaran and further with Chen with the second insulation layer including silicon nitride to benefit from providing a diffusion barrier preventing metal diffusion, while providing adhesion between metal and dielectric (Chen, ¶ 28, II. 1-7).
Claims 5-7, 10-11 and 17-18 are rejected under 35 U.S.C. § 103 as being unpatentable over Gambino Figs 1A-3A in view of Fig 1 further in view of Sukumaran and further in view of Lin et al (US 2014/0264911).
Regarding Claim 5, Gambino Figs 1A-3A in view of Gambino Fig 1 and further in view of Sukumaran discloses the limitations of Claim 1, however Gambino as modified does not disclose wherein the thermal pad further comprising a third insulation layer between the second insulation layer and the thermal core.
Instead, Lin (In Fig 1) teaches wherein the thermal pad further comprising a third insulation layer (466) between the second insulation layer (462) and the thermal core (470).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumaran and further with Lin with the thermal pad further comprising a third insulation layer between the second insulation layer and the thermal core to benefit from providing electrical isolation between TSV and the substrate (Lin, ¶ 19, II. 1-2).
Regarding Claim 6, Gambino Figs 1A-3A in view of Gambino Fig 1 further in view of Sukumaran and further in view of Lin discloses the limitations of Claim 5, however Gambino as modified does not disclose wherein the third insulation layer includes an oxide.
Instead, Lin (In Fig 1) further teaches wherein the third insulation layer (466) includes an oxide (¶ 19, II. 6-13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumaran and further with Lin with the third insulation layer including Oxide to benefit from providing electrical isolation between TSV and the substrate (Lin, ¶ 19, II. 1-2).
Regarding Claim 7, Gambino Figs 1A-3A in view of Gambino Fig 1 further in view of Sukumaran and further in view of Lin discloses the limitations of Claim 5, however Gambino as modified does not disclose wherein the third insulation layer is entirely within the trench.
Instead, Lin (In Fig 1) further teaches wherein the third insulation (466) layer is entirely within the trench (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumaran and further with Lin with the third insulation layer being entirely within the trench to benefit from providing electrical isolation between TSV and the substrate (Lin, ¶ 19, II. 1-2).
Regarding Claim 10, Gambino Figs 1A-3A in view of Gambino Fig 1 and further in view of Sukumaran discloses the limitations of Claim 8, however Gambino as modified does not disclose wherein the semiconductor chip further comprising a third insulation layer between the second insulation layer and the thermal core.
Instead, Lin (In Fig 1) teaches wherein the semiconductor chip further comprising a third insulation layer (466) between the second insulation layer (462) and the thermal core (470).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumaran and further with Lin with the semiconductor chip further comprising a third insulation layer between the second insulation layer and the thermal core to benefit from providing electrical isolation between TSV and the substrate (Lin, ¶ 19, II. 1-2).
Regarding Claim 11, Gambino Figs 1A-3A in view of Gambino Fig 1 further in view of Sukumaran and further in view of Lin discloses the limitations of Claim 10, however Gambino as modified does not disclose wherein the third insulation layer is entirely within the trench.
Instead, Lin (In Fig 1) further teaches wherein the third insulation (466) layer is entirely within the trench (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumaran and further with Lin with the third insulation layer being entirely within the trench to benefit from providing electrical isolation between TSV and the substrate (Lin, ¶ 19, II. 1-2).
Regarding Claim 17, Gambino Figs 1A-3A in view of Gambino Fig 1 and further in view of Sukumaran discloses the limitations of Claim 15, however Gambino as modified does not disclose wherein the thermal pad further comprising a third insulation layer between the second insulation layer and the thermal core.
Instead, Lin (In Fig 1) teaches wherein the thermal pad further comprising a third insulation layer (466) between the second insulation layer (462) and the thermal core (470).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumaran and further with Lin with the thermal pad further comprising a third insulation layer between the second insulation layer and the thermal core to benefit from providing electrical isolation between TSV and the substrate (Lin, ¶ 19, II. 1-2).
Regarding Claim 18, Gambino Figs 1A-3A in view of Gambino Fig 1 further in view of Sukumaran and further in view of Lin discloses the limitations of Claim 17, however Gambino as modified does not disclose wherein the third insulation layer is entirely within the trench.
Instead, Lin (In Fig 1) further teaches wherein the third insulation (466) layer is entirely within the trench (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumaran and further with Lin with the third insulation layer being entirely within the trench to benefit from providing electrical isolation between TSV and the substrate (Lin, ¶ 19, II. 1-2).
Claim 12 is rejected under 35 U.S.C. § 103 as being unpatentable over Gambino Figs 1A-3A in view of Fig 1 further in view of Sukumara and further in view of Kuo et al (US 2009/0160058).
Regarding Claim 12, Gambino Figs 1A-3A in view of Gambino Fig 1 and further in view of Sukumara discloses the limitations of Claim 8, however Gambino as modified does not disclose wherein the semiconductor chip further comprising a head portion protruding from the lower surface of the semiconductor substrate on the TSV.
Instead, Kuo (In Fig 8) teaches wherein the semiconductor chip further comprising a head portion (52) protruding from the lower surface of the semiconductor substrate (2) on the TSV (50), (Fig 8).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumara and further with Kuo with a head portion protruding from the lower surface of the semiconductor substrate to benefit from providing a platform for attachment of solder bump and the semiconductor die (Kuo, ¶ 36, II. 5-7).
Claim 13 is rejected under 35 U.S.C. § 103 as being unpatentable over Gambino Figs 1A-3A in view of Fig 1 further in view of Sukumara further in view of Kuo and further in view of Chun et al (US 2013/0264720).
Regarding Claim 13, Gambino Figs 1A-3A in view of Gambino Fig 1 further in view of Sukumara and further in view of Kuo discloses the limitations of Claim 12, however Gambino as modified does not disclose wherein the semiconductor chip further comprising a seed layer between the TSV and the head portion.
Instead, Chun (In Fig 5B) teaches wherein the semiconductor chip further comprising a seed layer (162a) between the TSV (140) and the head portion (160d), (Fig 5B).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumara further with Kuo and further with Chun with a seed layer between the TSV and the head portion to benefit from forming the plated pad on the seed layer, thereby forming electrical conduction (Chun, ¶ 44, II. 4-7).
Claim 14 is rejected under 35 U.S.C. § 103 as being unpatentable over Gambino Figs 1A-3A in view of Fig 1 further in view of Sukumara and further in view of Moon et al (US 2014/0035164).
Regarding Claim 14, Gambino Figs 1A-3A in view of Gambino Fig 1 and further in view of Sukumara discloses the limitations of Claim 8, however Gambino as modified does not disclose wherein the semiconductor chip further comprising a fourth insulation layer on the lower surface of the semiconductor substrate and surrounding the TSV and the thermal head.
Instead, Moon (In Fig 1A) teaches wherein the semiconductor chip further comprising a fourth insulation layer (32/38) on the lower surface of the semiconductor substrate (10) and surrounding the TSV (28) and the thermal head (36/40), (Fig 1A).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Gambino Figs 1A-3A with Fig 1 further with Sukumara and further with moon with a fourth insulation layer on the lower surface of the semiconductor substrate and surrounding the TSV and the thermal head to benefit from providing a desired conductive line formed onto the via with high quality of contact with low resistance and high current capacity (Moon, ¶ 6, II. 1-5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; Backside Heat Dissipation Using Buried Heat Rails US 2023/0187300, Integrated Circuit Structure Having Through-Silicon Via and Method of Forming Same US 9805977, Multilayer High-K Dielectric for a High Performance Logic Transistor US 2021/0167182, Semiconductor Device and Structure for Heat Removal US 2012/0306082. Other pertinent art made of record are on form PTO-892 notice of reference cited.
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/AMIR A JALALI/Primary Examiner, Art Unit 2841
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