Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. In the event that the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. US2014/0146461.
Per claim 1 Choi et al. teaches an apparatus (see fig.3, “everything inside 100a”), comprising: a memory device (114; [0049]) coupled to a first area of a circuit board (see fig.3, “left side”); a power regulation area (132, see fig.2B, [0050], “area with 150”) coupled to a second area of the circuit board (see fig.3, “right side”); and a thermal insulating barrier (140a; [0063], [0055]) deployed between the memory device and the power regulation area (see fig.3).
Per claim 2 Choi et al. teaches the apparatus of claim 1, wherein the circuit board is a solid state drive (SSD) ([0036]-[0037], [0061]).
Per claim 3 Choi et al. teaches the apparatus of claim 2, further comprising a controller ([0041]) resident on the SSD, wherein the thermal insulating barrier (140a) is deployed between the controller and the memory device (see fig.3).
Per claim 4 Choi et al. teaches the apparatus of claim 1, further comprising a plurality of heat sinks (132 & 134; [0046]-[0047], “the housings act as heat dissipation structures which Examiner equates to heat sink, consistent with Applicants definition of a heat sink”) coupled to the apparatus (see fig.3), wherein the thermal insulating barrier (140a) is disposed between at least two of the plurality of heat sinks (see fig.3).
Per claim 5 Choi et al. teaches the apparatus of claim 1, wherein at least a portion of the thermal insulating barrier extends through a heat sink associated with the apparatus (see fig.3).
Per claim 6 Choi et al. teaches the apparatus of claim 1, wherein the first area is on a first side of the thermal insulating barrier and the second area is on a second side of the thermal insulating barrier (see fig.3).
Per claim 7 Choi et al. teaches the apparatus of claim 1, wherein the memory device is a non-volatile memory device (114; [0041]), and wherein the thermal insulating barrier (140a) is to reduce heat transfer from the power regulation area to the non-volatile memory device ([0055], [0059]).
Per claim 8 Choi et al. teaches the apparatus of claim 1, wherein the thermal insulating barrier comprises an air gap or a thermally insulting material ([0055]), or both.
Claim Rejections - 35 USC § 103
2. In the event that the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. US2014/0146461 in view of Choi et al. US2014/0146461 in a second embodiment.
Per claim 9 Choi et al. teaches an apparatus, comprising: a printed circuit board (PCB) (120); a controller (112; [0041]) coupled to the PCB (see fig.3); a memory device area including non-volatile memory devices ([0041]); a power regulation area (132, see fig.2B; [0050], “area with 150”) coupled to the PCB (see fig.3); and a thermal insulating barrier (140a) coupled to the PCB (see fig.3), wherein the thermal insulating barrier is deployed between the controller, the power regulation area, and the memory device area (see fig.3).
Choi et al. does not explicitly teach a volatile memory device coupled to the PCB
Choi et al. in a second embodiment however discloses a volatile memory device (416) coupled to the PCB (see fig.3).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have a volatile memory device as taught by Choi et al. in a second embodiment in the apparatus of Choi et al., because it enables fast processing of data via the volatile memory device.
Per claim 11 Choi et al. in view of Choi et al. embodiment 2 teaches the apparatus of claim 9, wherein the controller, the power regulation area, and the memory device area are disposed on a top portion of the PCB (see fig.3).
Per claim 12 Choi et al. in view of Choi et al. embodiment 2 teaches the apparatus of claim 9, wherein the thermal insulating barrier is deployed to prevent heat transfer between the controller, the power regulation area, and the memory device area ([0055]).
Allowable Subject matter
3. Claims 10, 13-16 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10, includes allowable subject matter because of the apparatus of claim 9, further comprising a monolithic heat sink coupled to the PCB, wherein the thermal insulating barrier is formed entirely through the monolithic heat sink such that at least a portion of the thermal insulating barrier extends around a bottom portion of the PCB, or below a bottom portion of the PCB, or both.
Claim 13, includes allowable subject matter because of the apparatus of claim 9, further comprising a monolithic heat sink coupled to the PCB, wherein the thermal insulating barrier is formed through at least a portion of the monolithic heat sink.
Claim 14, includes allowable subject matter because of the apparatus of claim 9, wherein the controller and the power regulation area are disposed on a top portion of the PCB and at least one of the non-volatile memory device and the volatile memory device are disposed on a bottom portion of the PCB.
Per claim 15-16, depends on claim 14 therefore allowable for the same reason.
Claims 17-20 are allowable
4. Regarding Independent claim 17, patentability exists, at least in part, with the claimed combination of elements and features of: an apparatus, comprising: a memory sub-system, the memory sub-system comprising: a printed circuit board (PCB); a controller; a power regulation area; a non-volatile memory device; a volatile memory device; a heat sink; and a thermal insulating barrier, wherein the thermal insulating barrier is formed through at least a portion of the heat sink to separate a first physical contact point with the controller, a second physical contact point with the power regulation area, and a third physical contact point with at least one of the non-volatile memory device and the volatile memory device.
Claims 18-20 are dependent on claim 17, therefore allowable for the same reason.
Email Communication
5. Applicant is encouraged to authorize the Examiner to communicate via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502, 502.05.
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoshihara US2022/0312627 discloses a memory system comprising; a first substrate having a first surface side; a first semiconductor device on the first surface side of the first substrate in a first area; a second semiconductor device on the first surface side of the first substrate in a second area spaced from the first area in a first direction.
Lee US2018/0107540 discloses a data storage apparatus.
Applicants are directed to consider additional pertinent prior are included on the Notice of References Cited (PTOL 892) attached herewith. The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Applicant, in preparing the response, should consider fully the entire reference as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A MATEY whose telephone number is (571)270-5648. The examiner can normally be reached Monday-Friday 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAYPRAKASH GANDHI can be reached at 5712723740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL A MATEY/Primary Examiner, Art Unit 2841
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