DETAILED ACTION
This action is responsive to the response filed 30 Oct 2024 and the Information Disclosure Statement filed 15 Apr 2026. Claims 1-20 are pending. Claims 1, 7 and 18 are independent. The
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 15 Apr 2026 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation - 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Such claim limitation(s) is/are:
Claim(s) 18-20: all use the limitation “means for”
Claim Interpretation - 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Such claim limitation(s) is/are:
Claim(s) 18-20: all use the limitation “means for”
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3 – 7, 9 – 14, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bloemer, et al, U.S. Patent Application Publication 2022/0246183 (“Bloemer”).
Regarding claim 1, Bloemer teaches:
A memory comprising: a memory physical interface (PHY) of a memory coupled to a memory bus and (Bloemer, fig 1, 2, “[0036] FIG. 2 is a block diagram of a training architecture 200 for a memory device included in system memory 104 and/or parallel processing memory 134 of the computer system of FIG. 1, … When operating the memory device at higher speeds, the memory controller, such as system memory controller 130 and/or PPS memory controller 132, periodically performs these training operations”; a memory controller (i.e. host) 130 or 132 that has a CA interface to the system memory 104 (226) of fig 1).
configured to receive a received Pseudo-Random Binary Sequence (PRBS) through the memory bus from a host PHY; a PRBS generator configured to generate a generated PRBS; and (Bloemer, fig 2, “[0045] Upon entry into the command address training operation, the DRAM enters a first mode. The circuitry for each command address input pin 206 includes a CA LFSR 210 that generates a pseudo-random bit sequence (PRBS). The circuitry for each command address input pin 206 further includes a PRBS checker, such as XOR gate 212, that compares the PRBS generated by CA LFSR 210 with a PRBS received from the memory controller via receiver 208. [0046] By design, the memory controller and CA LFSR 210 generate the same PRBS.”; a memory controller (i.e. host) sends an LFSR PRBS to the input CA pins; the input LFSR is compared to an LFSR/ PRBS from the onboard CA LFSR 210).
compare logic configured to generate a score based on comparing the received PRBS to the generated PRBS, (Bloemer, fig 2, “[0037] The XOR gate 212 compares the data pattern on the CA input pins 206 with the data from the CA LFSR 210. The XOR gate 212 transmits a low value if the data pattern on the CA input pins 206 match the data from the CA LFSR 210. The XOR gate 212 transmits a high value if the data pattern on the CA input pins 206 does not match the data from the CA LFSR 210.”; the XOR gate 212 provides a ‘low value’ (i.e. low score) if the two data streams match and transmits a ‘high score’ if the two data streams do not match for each CA pin).
the memory PHY further configured to send the score to the host PHY. (Bloemer, fig 2, “[0037] The mode 204 input to multiplexor 202 selects the bottom input to transmit the output of the XOR gate 212 to transmitter 214 and then to one or more data (DQ), extended data (DQX), and/or error detection and correction (EDC) pins 216. The memory controller then reads the one or more DQ, DQX, and/or EDC pins 216 to determine whether the command address input training was successful. [0040] Once the data read training and data write training completes, the mode 204 input… transmit the output of the DRAM core 226 to transmitter 214 and then to one or more data (DQ), … pins 216.”; as the XOR gate 212 is providing the CA pin results, the scores from the CA, read, and write training from the multiplexor gate is sent back to the host controller via the DQ/DQX bus using TX 214. Note: Bloemer first trains the CA pins (i.e. 0037); second trains the read operation (i.e. 0038); and third trains the write operation (i.e. 0039)).
Regarding claim 3, Bloemer teaches The memory of claim 1, further comprising a Linear Feedback Shift Register (LFSR) configured to generate the generated PRBS. (Bloemer, fig 2, “[0045] Upon entry into the command address training operation, the DRAM enters a first mode. The circuitry for each command address input pin 206 includes a CA LFSR 210 that generates a pseudo-random bit sequence (PRBS).”; a memory that uses a LFSR to generate and evaluate the PRBS signals).
Regarding claim 4, Bloemer teaches The memory of claim 3, wherein the memory PHY is further configured to receive an initial seed for the LFSR from the host PHY through the memory bus before the generating the generated PRBS. (Bloemer, fig 2, “[0038] The memory controller causes a seed value and/or polynomial to be loaded into the read/write linear feedback shift register (R/W LFSR) 220. [0046] Further, the PRBS may be based on any technically feasible seed value and/or polynomial. Each CA LFSR 210 corresponding to each CA input pin 206 may be loaded with the same seed value and/or polynomial.”; that the memory controller can send a seed value to the LFSR; that the LFSR may use a seed value to generate the PRBS sequence used in testing).
Regarding claim 5, Bloemer teaches The memory of claim 1, wherein the compare logic is configured to generate a pass/fail score. (Bloemer, fig 2, “[0037] The XOR gate 212 compares the data pattern on the CA input pins 206 with the data from the CA LFSR 210. The XOR gate 212 transmits a low value if the data pattern on the CA input pins 206 match the data from the CA LFSR 210. The XOR gate 212 transmits a high value if the data pattern on the CA input pins 206 does not match the data from the CA LFSR 210.”; the XOR gate 212 provides a ‘low value’ (i.e. pass score) if the two data streams match and transmits a ‘high score’ (i.e. fail score) if the two data streams do not match for each CA pin).
Regarding claim 6, Bloemer teaches The memory of claim 1, further comprising a result store, wherein the memory PHY is configured to receive a memory refresh read (MRR) command from the host PHY through the memory bus and to read out the score from the result store and send the score through the memory bus in response to the MRR. (Bloemer, fig 2, “[0044] In some examples, the memory controller may transmit a command to the DRAM to load a register in the DRAM, such as a mode register, with a particular value that includes a command to enter a command address training operation. When the DRAM subsequently enters and then exits a low-power state, such as an idle state, a self-refresh state, and/or the like, the DRAM reads the mode register. If the value in the mode register includes a command to enter command address interface training, then the DRAM enters the command address training operation. If the value in the mode register does not include a command to enter command address interface training, then the DRAM does not enter the command address training operation.”; the memory receives a command to enter the “command address training operation” after a low operation state; low operation states include the refresh state; after exiting the refresh state, the memory automatically enters the command state; Bloemer’s training includes training the CA, read cycle, and write cycle; these cycles, as described in claim 1 generates a “score” for each process; and sends the score to the host. Note: the word “result” score has been interpreted as identical to the “score” claimed by claim 1).
Regarding claim 7, Bloemer teaches:
A method comprising: (Bloemer, fig 1, 2, “[0036] FIG. 2 is a block diagram of a training architecture 200 for a memory device included in system memory 104 and/or parallel processing memory 134 of the computer system of FIG. 1, … When operating the memory device at higher speeds, the memory controller, such as system memory controller 130 and/or PPS memory controller 132, periodically performs these training operations”; a memory controller (i.e. host) 130 or 132 that has a CA interface to the system memory 104 (226) of fig 1).
receiving a received Pseudo-Random Binary Sequence (PRBS) through a memory bus at a memory physical interface (PHY) from a host PHY; generating a generated PRBS at the memory PHY; (Bloemer, fig 2, “[0045] Upon entry into the command address training operation, the DRAM enters a first mode. The circuitry for each command address input pin 206 includes a CA LFSR 210 that generates a pseudo-random bit sequence (PRBS). The circuitry for each command address input pin 206 further includes a PRBS checker, such as XOR gate 212, that compares the PRBS generated by CA LFSR 210 with a PRBS received from the memory controller via receiver 208. [0046] By design, the memory controller and CA LFSR 210 generate the same PRBS.”; a memory controller (i.e. host) sends an LFSR PRBS to the input CA pins; the input LFSR is compared to an LFSR/ PRBS from the onboard CA LFSR 210).
comparing the received PRBS to the generated PRBS; generating a score based on comparing the received PRBS and the generated PRBS; and (Bloemer, fig 2, “[0037] The XOR gate 212 compares the data pattern on the CA input pins 206 with the data from the CA LFSR 210. The XOR gate 212 transmits a low value if the data pattern on the CA input pins 206 match the data from the CA LFSR 210. The XOR gate 212 transmits a high value if the data pattern on the CA input pins 206 does not match the data from the CA LFSR 210.”; the XOR gate 212 provides a ‘low value’ (i.e. low score) if the two data streams match and transmits a ‘high score’ if the two data streams do not match for each CA pin).
sending the score to the host PHY through the memory bus. (Bloemer, fig 2, “[0037] The mode 204 input to multiplexor 202 selects the bottom input to transmit the output of the XOR gate 212 to transmitter 214 and then to one or more data (DQ), extended data (DQX), and/or error detection and correction (EDC) pins 216. The memory controller then reads the one or more DQ, DQX, and/or EDC pins 216 to determine whether the command address input training was successful. [0040] [0040] Once the data read training and data write training completes, the mode 204 input… transmit the output of the DRAM core 226 to transmitter 214 and then to one or more data (DQ), … pins 216.”; as the XOR gate 212 is providing the CA pin results, the scores from the CA, read, and write training from the multiplexor gate is sent back to the host controller via the DQ/DQX bus using TX 214. Note: Bloemer first trains the CA pins (i.e. 0037); second trains the read operation (i.e. 0038); and third trains the write operation (i.e. 0039)).
Regarding claim 9, Bloemer teaches The method of claim 7, further comprising receiving a Memory Refresh Write (MRW) command from the host PHY to enable a write training mode at the memory PHY before the receiving the received PRBS. (Bloemer, fig 2, “[0044] In some examples, the memory controller may transmit a command to the DRAM to load a register in the DRAM, such as a mode register, with a particular value that includes a command to enter a command address training operation. When the DRAM subsequently enters and then exits a low-power state, such as an idle state, a self-refresh state, and/or the like, the DRAM reads the mode register. If the value in the mode register includes a command to enter command address interface training, then the DRAM enters the command address training operation. If the value in the mode register does not include a command to enter command address interface training, then the DRAM does not enter the command address training operation.”; the memory receives a command to enter the “command address training operation” after a low operation state; low operation states include the refresh state; after exiting the refresh state, the memory automatically enters the command state; Bloemer’s training includes training the CA, read cycle, and write cycle; these cycles, as described in claim 1 generates a “score” for each process; and sends the score to the host. Note: the word “result” score has been interpreted as identical to the “score” claimed by claim 1).
Regarding claim 10, Bloemer teaches The method of claim 7, wherein the generating the generated PRBS comprises generating the PRBS using a Linear Feedback Shift Register (LFSR). (Bloemer, fig 2, “[0045] Upon entry into the command address training operation, the DRAM enters a first mode. The circuitry for each command address input pin 206 includes a CA LFSR 210 that generates a pseudo-random bit sequence (PRBS).”; a memory that uses a LFSR to generate and evaluate the PRBS signals).
Regarding claim 11, Bloemer teaches The method of claim 10, further comprising receiving an initial seed for the LFSR from the host PHY before the generating the generated PRBS. (Bloemer, fig 2, “[0038] The memory controller causes a seed value and/or polynomial to be loaded into the read/write linear feedback shift register (R/W LFSR) 220. [0046] Further, the PRBS may be based on any technically feasible seed value and/or polynomial. Each CA LFSR 210 corresponding to each CA input pin 206 may be loaded with the same seed value and/or polynomial.”; that the memory controller can send a seed value to the LFSR; that the LFSR may use a seed value to generate the PRBS sequence used in testing).
Regarding claim 12, Bloemer teaches The method of claim 10, further comprising receiving an LFSR parameter from the host PHY before the generating the generated PRBS. (Bloemer, fig 2, “[0038] The memory controller causes a seed value and/or polynomial to be loaded into the read/write linear feedback shift register (R/W LFSR) 220. [0046] Further, the PRBS may be based on any technically feasible seed value and/or polynomial. Each CA LFSR 210 corresponding to each CA input pin 206 may be loaded with the same seed value and/or polynomial.”; that the memory controller can send a seed value to the LFSR; that the LFSR may use a seed value to generate the PRBS sequence used in testing).
Regarding claim 13, Bloemer teaches The method of claim 7, wherein the generating the score comprises generating a pass/fail score. (Bloemer, fig 2, “[0037] The XOR gate 212 compares the data pattern on the CA input pins 206 with the data from the CA LFSR 210. The XOR gate 212 transmits a low value if the data pattern on the CA input pins 206 match the data from the CA LFSR 210. The XOR gate 212 transmits a high value if the data pattern on the CA input pins 206 does not match the data from the CA LFSR 210.”; the XOR gate 212 provides a ‘low value’ (i.e. pass score) if the two data streams match and transmits a ‘high score’ (i.e. fail score) if the two data streams do not match for each CA pin).
Regarding claim 14, Bloemer teaches The method of claim 7, wherein the sending the score comprises receiving a memory refresh read (MRR) command from the host PHY to read out the score and sending the score through the memory bus in response to the MRR command. (Bloemer, fig 2, “[0044] In some examples, the memory controller may transmit a command to the DRAM to load a register in the DRAM, such as a mode register, with a particular value that includes a command to enter a command address training operation. When the DRAM subsequently enters and then exits a low-power state, such as an idle state, a self-refresh state, and/or the like, the DRAM reads the mode register. If the value in the mode register includes a command to enter command address interface training, then the DRAM enters the command address training operation. If the value in the mode register does not include a command to enter command address interface training, then the DRAM does not enter the command address training operation.”; the memory receives a command to enter the “command address training operation” after a low operation state; low operation states include the refresh state; after exiting the refresh state, the memory automatically enters the command state; Bloemer’s training includes training the CA, read cycle, and write cycle; these cycles, as described in claim 1 generates a “score” for each process; and sends the score to the host. Note: the word “result” score has been interpreted as identical to the “score” claimed by claim 1).
Regarding claim 18, Bloemer teaches:
A memory apparatus comprising: (Bloemer, fig 1, 2, “[0036] FIG. 2 is a block diagram of a training architecture 200 for a memory device included in system memory 104 and/or parallel processing memory 134 of the computer system of FIG. 1, … When operating the memory device at higher speeds, the memory controller, such as system memory controller 130 and/or PPS memory controller 132, periodically performs these training operations”; a memory controller (i.e. host) 130 or 132 that has a CA interface to the system memory 104 (226) of fig 1).
means for receiving a received Pseudo-Random Binary Sequence (PRBS) through a memory bus at a memory physical interface (PHY) from a host PHY; means for generating a generated PRBS at the memory PHY; (Bloemer, fig 2, “[0045] Upon entry into the command address training operation, the DRAM enters a first mode. The circuitry for each command address input pin 206 includes a CA LFSR 210 that generates a pseudo-random bit sequence (PRBS). The circuitry for each command address input pin 206 further includes a PRBS checker, such as XOR gate 212, that compares the PRBS generated by CA LFSR 210 with a PRBS received from the memory controller via receiver 208. [0046] By design, the memory controller and CA LFSR 210 generate the same PRBS.”; a memory controller (i.e. host) sends an LFSR PRBS to the input CA pins; the input LFSR is compared to an LFSR/ PRBS from the onboard CA LFSR 210).
means for generating a score based on comparing the received PRBS to the generated PRBS; and (Bloemer, fig 2, “[0037] The XOR gate 212 compares the data pattern on the CA input pins 206 with the data from the CA LFSR 210. The XOR gate 212 transmits a low value if the data pattern on the CA input pins 206 match the data from the CA LFSR 210. The XOR gate 212 transmits a high value if the data pattern on the CA input pins 206 does not match the data from the CA LFSR 210.”; the XOR gate 212 provides a ‘low value’ (i.e. low score) if the two data streams match and transmits a ‘high score’ if the two data streams do not match for each CA pin).
means for sending the score to the host PHY through the memory bus. (Bloemer, fig 2, “[0037] The mode 204 input to multiplexor 202 selects the bottom input to transmit the output of the XOR gate 212 to transmitter 214 and then to one or more data (DQ), extended data (DQX), and/or error detection and correction (EDC) pins 216. The memory controller then reads the one or more DQ, DQX, and/or EDC pins 216 to determine whether the command address input training was successful.”; as the XOR gate 212 is providing the CA pin results, the score from the gate is sent back to the host controller via the DQ/DQX bus using TX 214. Note: Bloemer first trains the CA pins (i.e. 0037); second trains the read operation (i.e. 0038); and third trains the write operation (i.e. 0039)).
Regarding claim 20, Bloemer teaches:
The memory apparatus of claim 18, further comprising means for generating a second generated PRBS at the memory PHY; and (Bloemer, fig 2, “[0038] The memory controller causes a seed value and/or polynomial to be loaded into the read/write linear feedback shift register (R/W LFSR) 220.”; the R/W LFSR generates a code on the memory; as stated previously, this code can be based on a seeded value).
means for sending the second generated PRBS in response to a read training command from the host PHY. (Bloemer, fig 2, “[0044] In some examples, the memory controller may transmit a command to the DRAM to load a register in the DRAM, such as a mode register, with a particular value that includes a command to enter a command address training operation. When the DRAM subsequently enters and then exits a low-power state, such as an idle state, a self-refresh state, and/or the like, the DRAM reads the mode register. If the value in the mode register includes a command to enter command address interface training, then the DRAM enters the command address training operation. If the value in the mode register does not include a command to enter command address interface training, then the DRAM does not enter the command address training operation.”; after exiting the refresh state, the memory automatically enters the command state; Bloemer’s training includes training the CA, read cycle, and write cycle; these cycles, as described in claim 1 generates a “code” which is sent to a comparator for testing the system for each process; and sends the score to the host).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Bloemer in view of Lee, et al, U.S. Patent Application Publication 2024/0005204 (“Lee”).
Regarding claim 2, Bloemer teaches the memory of claim 1.
Bloemer teaches wherein the memory bus comprises data lines and (Bloemer, fig 2, “[0039] Third, the memory controller performs training operations on the data write interface. [0049] If one or more of the DQ/DQX/EDC output pins 216 indicates a fail result value, then the memory controller adjusts the skew between the corresponding CA input pin 206 and the clock signal until a pass result value is consistently received for all CA input pins 206.”; that a device can perform CA, read, and write data training operations).
Bloemer has not been used to explicitly teach:
a write clock line and
wherein the memory PHY is configured to receive the PRBS through the data lines of the memory bus based on a timing of the write clock..
Lee more explicitly teaches:
a write clock line and (Lee, fig 7, “[0084] Referring to FIG. 7, upon the write training, the receiver 710 may receive a plurality of input write training patterns WT0, WT1, WTn-1. The plurality of samplers 711_0, 711_1, … , 711_n-1 may output sampling data SAD0, SAD1, … , SADn-1 by sampling the plurality of write training patterns WT0, WT1, … , WTn-1, respectively by synchronizing with the internal data clock ICK.”; a device can perform write training using data input through the DQ bus with an internal data clock (i.e. claimed write clock)).
wherein the memory PHY is configured to receive the PRBS through the data lines of the memory bus based on a timing of the write clock. (Lee, fig 4, 7, “[0072] The sequence data generator 410 may include a PRBS sequence data generator 411 and a scrambler 412. The PRBS sequence data generator 411 may generate PRBS data based on the seed value SV. When the plurality of latches 731_0, 732_1, … , 731_n-1 receives the read training command from the memory controller (110 in FIG. 1), the plurality of latches 731_0, 732_1, … , 731_n-1 may output the plurality of counting result values WTR0, WTR1, … , WTRn-1. to the plurality of data lines DQ0, DQl, … , DQn-1.”; a device transmits the results of a write test back to the memory controller via the DQ pins).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to Bloemer before the effective filing date of the claimed invention in order to teach memory testing. The teachings of Lee, in the same or in a similar field of endeavor with Bloemer, can combine Lee’s explicit training with a clock for write operations with Bloemer’s less explicit training with a clock during write operations. The two training methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 8, Bloemer teaches the method of claim 7.
Bloemer teaches wherein the receiving a received PRBS (Bloemer, fig 2, “[0039] Third, the memory controller performs training operations on the data write interface. [0049] If one or more of the DQ/DQX/EDC output pins 216 indicates a fail result value, then the memory controller adjusts the skew between the corresponding CA input pin 206 and the clock signal until a pass result value is consistently received for all CA input pins 206.”; that a device can perform write data training operations).
Bloemer does not explicitly teach comprises receiving the PRBS through data lines of the memory bus with a write clock..
Lee teaches comprises receiving the PRBS through data lines of the memory bus with a write clock. (Lee, fig 4, 7, “[0084] Referring to FIG. 7, upon the write training, the receiver 710 may receive a plurality of input write training patterns WT0, WT1, WTn-1. The plurality of samplers 711_0, 711_1, … , 711_n-1 may output sampling data SAD0, SAD1, … , SADn-1 by sampling the plurality of write training patterns WT0, WT1, … , WTn-1, respectively by synchronizing with the internal data clock ICK. … [0072] The sequence data generator 410 may include a PRBS sequence data generator 411 and a scrambler 412. The PRBS sequence data generator 411 may generate PRBS data based on the seed value SV. When the plurality of latches 731_0, 732_1, … , 731_n-1 receives the read training command from the memory controller (110 in FIG. 1), the plurality of latches 731_0, 732_1, … , 731_n-1 may output the plurality of counting result values WTR0, WTR1, … , WTRn-1. to the plurality of data lines DQ0, DQl, … , DQn-1.”; a device can perform write training using data input through the DQ bus with an internal data clock (i.e. claimed write clock); a device transmits the results of a write test back to the memory controller via the DQ pins).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to Bloemer before the effective filing date of the claimed invention in order to teach memory testing. The teachings of Lee, in the same or in a similar field of endeavor with Bloemer, can combine explicit training with a clock for write operations with Bloemer’s less explicit training with a clock during write operations. The two training methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 15 – 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bloemer in view of Kang, et al, U.S. Patent Application Publication 2025/0364070 (“Kang”).
Regarding claim 15, Bloemer teaches the method of claim 14.
Bloemer teaches further comprising: (Bloemer, fig 2, “[0039] The output of the XOR gate 222 is transmitted to the write training result register 224 and stored as pass/fail write training status for each of the DQ, DQX, and/or EDC pins 216 undergoing write training.”; a memory that can perform a read/ write training result and transmit the score to a host).
Bloemer does not explicitly teach storing the score in a result store; and sending the score from the result store..
Kang teaches storing the score in a result store; and sending the score from the result store. (Kang, fig 1, 2, 4, 11, “[0071] Based on passing the write test or the read test, the memory controller 120 may control the memory device 110 to store the test results in the memory device 110, and control the memory device 110 to perform a write operation and/or a read operation. [0104] The read test result DQ READ TEST P/F DATA 930 may be transmitted to an external host.”; that write and read data can be stored by the memory controller; that the results of the read test can be transmitted to an external host).
In view of the teachings of Kang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kang to Bloemer before the effective filing date of the claimed invention in order to teach memory testing. The teachings of Kang, in the same or in a similar field of endeavor with Bloemer, can combine Kang’s explicit read/write training results storage with Bloemer’s less explicit read/write operations. The two training methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 16, Bloemer, as modified by Kang, teaches the method of claim 15.
Kang further teaches wherein the result store comprises configuration and status registers of the memory. (Kang, fig 1, 2, 4, 11, “[0104] As a result of the comparison, the first comparator 126 may generate a read test result DQ READ TEST P/F DATA 930 for each of the plurality of data lines DQ0, … , DQn-1. The read test result DQ READ TEST P/F DATA930 may be transmitted to an external host.”; that the data stored in claim 15 can comprise information about each of the DQ data lines).
In view of the teachings of Kang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kang to Bloemer before the effective filing date of the claimed invention in order to teach memory testing. The teachings of Kang, in the same or in a similar field of endeavor with Bloemer, can combine Kang’s explicit read/write training results storage with Bloemer’s less explicit read/write operations. The two training methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 17, Bloemer teaches the method of claim 7.
Bloemer teaches further comprising: receiving a read training command from the host PHY through the memory bus; generating a generated read PRBS at the memory PHY; and (Bloemer, fig 2, “[0044] In some examples, the memory controller may transmit a command to the DRAM to load a register in the DRAM, such as a mode register, with a particular value that includes a command to enter a command address training operation. When the DRAM subsequently enters and then exits a low-power state, such as an idle state, a self-refresh state, and/or the like, the DRAM reads the mode register. If the value in the mode register includes a command to enter command address interface training, then the DRAM enters the command address training operation. If the value in the mode register does not include a command to enter command address interface training, then the DRAM does not enter the command address training operation.”; the memory receives a command to enter the “command address training operation” after a low operation state; low operation states include the refresh state; after exiting the refresh state, the memory automatically enters the command state; Bloemer’s training includes training the CA, read cycle, and write cycle; these cycles, as described in claim 1 generates a “score” for each process; and sends the score to the host. Note: the word “result” score has been interpreted as identical to the “score” claimed by claim 1).
Bloemer does not explicitly teach sending the generated read PRBS to the host PHY with a read clock strobe through the memory bus..
Kang teaches sending the generated read PRBS to the host PHY with a read clock strobe through the memory bus. (Kang, fig 1, 2, 4, 11, “[0042] The memory controller 120 may apply a system clock CK and a data clock WCK to the memory device 110 to control data input and output. … Meanwhile, the data clock WCK may be a clock related to an input and output rate of the data DATA. The command CMD and the address ADDR may be transmitted based on the system clocks CK and CKB. In an example, the data DATA may be transmitted based on the data clock WCK.”; that the data clock (for both input/ output) can be sent to the host).
In view of the teachings of Kang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kang to Bloemer before the effective filing date of the claimed invention in order to teach memory testing. The teachings of Kang, in the same or in a similar field of endeavor with Bloemer, can combine Kang’s explicit read/write training results storage with Bloemer’s less explicit read/write operations. The two training methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 19, Bloemer teaches the memory apparatus of claim 18.
Bloemer teaches further comprising (Bloemer, fig 2, “ [0040] Once the data read training and data write training completes, the mode 204 input… transmit the output of the DRAM core 226 to transmitter 214 and then to one or more data (DQ), … pins 216.”; that the system can perform read and write tests for the input/output pins).
Bloemer does not explicitly teach means for storing the score, wherein the means for sending the score to the host PHY comprises means for receiving a memory refresh read command from the host PHY, reading the score from the means for storing and for sending the score in response to the MRR command..
Kang teaches means for storing the score, wherein the means for sending the score to the host PHY comprises means for receiving a memory refresh read command from the host PHY, reading the score from the means for storing and for sending the score in response to the MRR command. (Kang, fig 1, 2, 4, 11, “[0071] Based on passing the write test or the read test, the memory controller 120 may control the memory device 110 to store the test results in the memory device 110, and control the memory device 110 to perform a write operation and/or a read operation. [0104] The read test result DQ READ TEST P/F DATA 930 may be transmitted to an external host.”; that write and read data can be stored by the memory controller; that the results of the read test can be transmitted to an external host).
In view of the teachings of Kang it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kang to Bloemer before the effective filing date of the claimed invention in order to teach memory testing. The teachings of Kang, in the same or in a similar field of endeavor with Bloemer, can combine Kang’s explicit read/write training results storage with Bloemer’s less explicit read/write operations. The two training methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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