Prosecution Insights
Last updated: July 17, 2026
Application No. 18/932,586

MEMORY PERFORMING TARGET REFRESH OPERATION AND OPERATING METHOD OF MEMORY

Non-Final OA §102
Filed
Oct 30, 2024
Priority
Aug 27, 2024 — RE 10-2024-0115357
Examiner
NGUYEN, VIET Q
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1194 granted / 1256 resolved
+27.1% vs TC avg
Minimal +4% lift
Without
With
+3.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
26 currently pending
Career history
1272
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
31.7%
-8.3% vs TC avg
§102
37.1%
-2.9% vs TC avg
§112
16.2%
-23.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1256 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 1. Claims 1-17 are present for examination. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 2. Claims 1-4, 6-7 & 13-16 are rejected under 35 U.S.C. 102(a)(1) as being by anticipated by Kim (US 2019/0087127). Claim 1, 7 & 13 -15, Kim (Fig. 2) shows a cell array (or banks 1 to N), and Fig. 3 shows a control logic 110 for handing both target refreshing and hammer refreshing functions using the refresh command (REF) and the target refresh addresses (RADD) for refreshing a target row. Additionally, para [0053] stated the target refresh address (for a selected row) is also based on a quantity (or count) of active command operations and an error history (or number of error corrections for each row). Claim 2-4, 6, 16, Fig.4 shows an “error storage unit 440” as an error log for storing an error history including information collected (from the error counter 430), see [0067-0068], during an error check operation of the memory. Additionally, the “address selection unit 410” acts as the claimed ”access count region” for storing the quantity of the active operations (or #commands ACT) as claimed. See [0053-0058] below: PNG media_image1.png 302 1010 media_image1.png Greyscale PNG media_image2.png 314 904 media_image2.png Greyscale Claims 13-15, the precharging operation of any row is briefly mentioned in para [0006] as well-known to a skilled person in this art. 3. Claims 1-4, 6-10 & 12-16 are rejected under 35 U.S.C. 102(a)(1) as being by anticipated by Pan (US 2022/0165347). Claim 1, 7 & 13 -15, Pan (Fig. 1-3) shows a cell array (or banks 1 to 15), and a control logic (i.e., 102, 104, 106, 108, & 112-116) for handing both target refreshing and hammer refreshing functions using the refresh command (REF) and the target refresh addresses (RADD) for refreshing a target row. Additionally, Fig. 1 shows that each bank has both a normal cell region (NL1 to BL4 columns) and an “access count cell region”, or column BLN, for storing the quantity of active operations for each row. Claims 8-10, Fig. 1 also shows that the access count region for storing normal cells have same row quantity (WL1-WLm) with the access count region (126) for storing error history, but the normal cell region has more columns (= 4 columns or BL1-BL4) than the error history region (= 1 column or BLN). Claim 2-4, 6, 16, para [0017-000020] further stated that “the access count value memory cells may further store error correction code (ECC) information”, thus inherently suggest to a skilled person in this art that these extra count cells could also be configured to store the error history for each access row too. See [0017-0020] below. PNG media_image3.png 308 978 media_image3.png Greyscale Claims 13-15, the precharging operation of any row is briefly mentioned in para [0006] as well-known to a skilled person in this art. See [0028-0031] below: PNG media_image4.png 550 908 media_image4.png Greyscale 4. Claims 1-2, 7 & 15-16 are rejected under 35 U.S.C. 102(a)(1) as being by anticipated by KIM et al (US 2022/0246201). Claim 1-2, 7 & 13-16, Kim (Fig. 7) shows a cell array (or banks 110), and a control logic (i.e., 120-150) for handing both target refreshing and hammer refreshing functions using the refresh command (CMD) and the target refresh addresses (REF-ADDR) for refreshing a target row. Additionally, para [0091] stated that the “status register 220” is used to store the “number of activation commands”, and that para [0092] further mentions that the “number of error corrections” is stored as “error-corrected codewords” in the method step (S23) in Fig. 9-10, thus inherently suggests to a skilled person both the claimed stage means for storing the “a quantity of active operations” (of claim 3) and the “error history” (of claim 4) as well. See [0091-0092] below: PNG media_image5.png 438 1072 media_image5.png Greyscale Allowable Subject Matter 5. Claims 5, 7 & 11 are objected as being dependent upon their parent/rejected claims above, but they tentatively contain other novel limitations, (i.e., anticivilization periods of the error history region), to the recited structure above, which are not clearly suggested by the prior arts nor seen elsewhere at this time. 6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VIET Q NGUYEN/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Oct 30, 2024
Application Filed
Jun 05, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+3.5%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1256 resolved cases by this examiner. Grant probability derived from career allowance rate.

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