DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in this office action and presented for examination.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
In paragraph [00012], line 8, “after” may have been intended to be capitalized and possibly a start of a new paragraph.
In paragraph [00030], fourth-to-last line, a space should be inserted between ‘“/”’ and ‘generally’.
In paragraph [00048], line 3, “configured to as” may have been intended to be “configured as”.
Drawings
The drawings are objected to because:
Drawings shall be executed in durable, black, sufficiently dense and dark, uniformly thick and well-defined, lines and strokes without colorings. However, at least FIG. 2 does not meet this requirement.
The height of the numbers and letters shall not be less than 0.32 cm. However, at least FIG. 2 and FIG. 3 do not meet this requirement.
In FIG. 1, it is unclear as to whether “DRAWINGS” is intended to be part of FIG. 1.
In FIG. 2, “weigh” may have intended to be “weight”.
In FIG. 2, text appears to mingle with the bottom side of various rectangles, leading to a further lack of clarity.
In FIG. 5, “interfce” should be “interface”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “setting MCR (Move to Coprocessor from arm Register) instructions and a Coprocessor Data Processing instruction (CDP) with operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator” in lines 2-5. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means to “set” MCR instructions and a CDP instruction. For example, it is indefinite as to whether the limitation entails setting MCR instructions alongside setting operators of the recurrent neural network, or whether setting MCR instructions entails setting operators of the recurrent neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the limitation entails setting a CDP instruction alongside setting operators of the recurrent neural network, or whether setting a CDP instruction entails setting operators of the recurrent neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the operators of the recurrent neural network are “set” or not.
Claims 2-8 and 10 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 2 recites the limitation "configuring … stride block information to the scale register" in lines 6-8. Claim 2 further recites the limitation "configuring … the stride block information to the scale register" in lines 9-12. Claim 2 further recites the limitation "configuring … the stride block information to the scale register" in lines 13-15. Therefore, it is indefinite as to whether the step of claim 2, lines 4-5, indeed entails configuring the same information to the same register three times, or whether other behavior is intended to be conveyed by the limitations.
Claim 2 recites the limitation “the third MCR instructions” in line 13. However, there is insufficient antecedent basis for this limitation in the claims.
Claims 3-7 are rejected for failing to alleviate the rejections of claim 2 above.
Claim 3 recites the limitation “The method according to claim 2, wherein … the method further comprises: executing an operation using the matrix multiplication operator of the recurrent neural network …” in lines 1-7. Claim 1, upon which claim 3 is indirectly dependent, recites the limitation “A method … comprising: … executing an operation using one of the operators of the recurrent neural network” in lines 1-8. Therefore, it is indefinite as to whether “an operation” of claim 3 is the same as, or distinct from, “an operation” in claim 1, and consequently indefinite as to whether claim 3 entails executing one operation or two operations.
Claim 3 recites the limitation “executing an operation using the matrix multiplication operator of the recurrent neural network through the Coprocessor Data Processing instruction, partitioning a matrix of the feature data according to the stride block information, and partitioning a matrix of the weight data according to a preset weight quantity; and performing a corresponding multiply and accumulate operation on the partitioned matrix of the feature data and the partitioned matrix of the weight data according to the operation mode” in lines 6-11. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing an operation using the matrix multiplication operator of the recurrent neural network through the Coprocessor Data Processing instruction” is the same as, or distinct from, “partitioning a matrix of the feature data according to the stride block information, and partitioning a matrix of the weight data according to a preset weight quantity; and performing a corresponding multiply and accumulate operation on the partitioned matrix of the feature data and the partitioned matrix of the weight data according to the operation mode”. Similarly, it is indefinite as to whether the aforementioned “partitioning a matrix of the feature data according to the stride block information, and partitioning a matrix of the weight data according to a preset weight quantity; and performing a corresponding multiply and accumulate operation on the partitioned matrix of the feature data and the partitioned matrix of the weight data according to the operation mode” is the same as, or distinct from, the “executing an operation” step of claim 1, line 8.
Claim 4 recites the limitation “The method according to claim 2, wherein … the method further comprises: executing an operation using the vector arithmetic operator of the recurrent neural network …” in lines 1-6. Claim 1, upon which claim 4 is indirectly dependent, recites the limitation “A method … comprising: … executing an operation using one of the operators of the recurrent neural network” in lines 1-8. Therefore, it is indefinite as to whether “an operation” of claim 4 is the same as, or distinct from, “an operation” in claim 1, and consequently indefinite as to whether claim 4 entails executing one operation or two operations.
Claim 4 recites the limitation “executing an operation using the vector arithmetic operator of the recurrent neural network through the Coprocessor Data Processing instruction, and adding or multiplying values in the first vector set and the second vector set one by one according to the stride block information; and writing an arithmetic result back to a local buffer according to the write-back information” in lines 6-10. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing an operation using the vector arithmetic operator of the recurrent neural network through the Coprocessor Data Processing instruction” is the same as, or distinct from, “adding or multiplying values in the first vector set and the second vector set one by one according to the stride block information; and writing an arithmetic result back to a local buffer according to the write-back information”. Similarly, it is indefinite as to whether the aforementioned “adding or multiplying values in the first vector set and the second vector set one by one according to the stride block information; and writing an arithmetic result back to a local buffer according to the write-back information” is the same as, or distinct from, the “executing an operation” step of claim 1, line 8.
Claim 5 recites the limitation “The method according to claim 2, wherein … the method further comprises: executing an operation using the sigmoid activation operator of the recurrent neural network …” in lines 1-5. Claim 1, upon which claim 5 is indirectly dependent, recites the limitation “A method … comprising: … executing an operation using one of the operators of the recurrent neural network” in lines 1-8. Therefore, it is indefinite as to whether “an operation” of claim 5 is the same as, or distinct from, “an operation” in claim 1, and consequently indefinite as to whether claim 5 entails executing one operation or two operations.
Claim 5 recites the limitation “executing an operation using the sigmoid activation operator of the recurrent neural network through the Coprocessor Data Processing instruction, inputting the input data into a sigmoid activation function [equation] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information” in lines 5-9. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing an operation using the sigmoid activation operator of the recurrent neural network through the Coprocessor Data Processing instruction” is the same as, or distinct from, “inputting the input data into a sigmoid activation function [equation] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information”. Similarly, it is indefinite as to whether the aforementioned “inputting the input data into a sigmoid activation function [equation] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information” is the same as, or distinct from, the “executing an operation” step of claim 1, line 8.
Claim 6 recites the limitation “The method according to claim 2, wherein … the method further comprises: executing an operation using the tanh activation operator of the recurrent neural network …” in lines 1-5. Claim 1, upon which claim 6 is indirectly dependent, recites the limitation “A method … comprising: … executing an operation using one of the operators of the recurrent neural network” in lines 1-8. Therefore, it is indefinite as to whether “an operation” of claim 6 is the same as, or distinct from, “an operation” in claim 1, and consequently indefinite as to whether claim 6 entails executing one operation or two operations.
Claim 6 recites the limitation “executing an operation using the tanh activation operator of the recurrent neural network through the Coprocessor Data Processing instruction, inputting the input data into a tanh activation function [equation] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information” in lines 5-9. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing an operation using the tanh activation operator of the recurrent neural network through the Coprocessor Data Processing instruction” is the same as, or distinct from, “inputting the input data into a tanh activation function [equation] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information”. Similarly, it is indefinite as to whether the aforementioned “inputting the input data into a tanh activation function [equation] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information” is the same as, or distinct from, the “executing an operation” step of claim 1, line 8.
Claim 7 recites the limitation “The method according to claim 2, wherein … the method further comprises: executing an operation using the quantization operator of the recurrent neural network …” in lines 1-5. Claim 1, upon which claim 7 is indirectly dependent, recites the limitation “A method … comprising: … executing an operation using one of the operators of the recurrent neural network” in lines 1-8. Therefore, it is indefinite as to whether “an operation” of claim 7 is the same as, or distinct from, “an operation” in claim 1, and consequently indefinite as to whether claim 7 entails executing one operation or two operations.
Claim 7 recites the limitation “executing an operation using the quantization operator of the recurrent neural network through the Coprocessor Data Processing instruction, and converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard in the input data into a 16-bit integer according to the stride block information, or converting a 16-bit integer in the input data into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard; and writing a conversion result back to a local buffer according to the write-back information” in lines 5-10. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing an operation using the quantization operator of the recurrent neural network through the Coprocessor Data Processing instruction” is the same as, or distinct from, “converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard in the input data into a 16-bit integer according to the stride block information, or converting a 16-bit integer in the input data into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard; and writing a conversion result back to a local buffer according to the write-back information”. Similarly, it is indefinite as to whether the aforementioned “converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard in the input data into a 16-bit integer according to the stride block information, or converting a 16-bit integer in the input data into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard; and writing a conversion result back to a local buffer according to the write-back information” is the same as, or distinct from, the “executing an operation” step of claim 1, line 8.
Claim 8 recites the limitation “executing a data reading operation through the Coprocessor Data Processing instruction, and reading data in the main memory address into the local buffer according to the stride block information” in lines 4-6. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing a data reading operation through the Coprocessor Data Processing instruction” is the same as, or distinct from, “reading data in the main memory address into the local buffer according to the stride block information”.
Claim 8 recites the limitation “executing a data writing operation through the Coprocessor Data Processing instruction, and writing data in the local buffer into the main memory address according to the stride block information” in lines 7-9. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing a data writing operation through the Coprocessor Data Processing instruction” is the same as, or distinct from, “writing data in the local buffer into the main memory address according to the stride block information”.
Claim 9 recites the limitation “sets MCR instructions and a Coprocessor Data Processing instruction with operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator” in lines 3-6. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means to “set” MCR instructions and a Coprocessor Data Processing instruction. For example, it is indefinite as to whether the limitation entails setting MCR instructions alongside setting operators of the recurrent neural network, or whether setting MCR instructions entails setting operators of the recurrent neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the limitation entails setting a Coprocessor Data Processing instruction alongside setting operators of the recurrent neural network, or whether setting a Coprocessor Data Processing instruction entails setting operators of the recurrent neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the operators of the recurrent neural network are “set” or not.
Claim 9 recites the limitation “executes an operation using the common basic operators of the recurrent neural network through the Coprocessor Data Processing instruction on the basis of the configured internal register” in lines 9-11. However, it is indefinite as to whether the recited [single] operation uses [all of] the common basic operators (e.g., a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator, and a quantization operator), or another interpretation is intended.
Claim 9 recites the limitation “the common basic operators of the recurrent neural network” in lines 9-10. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 9 recites the limitation “common basic operators” in lines 9-10. However, it is indefinite as to the criteria by which an operator (or a basic operator) would be considered to be “common”. Similarly, it is indefinite as to the criteria by which an operator (or a common operator) would be considered to be “basic”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ren et al. (CN 114298293 A) (hereafter referred to Ren ‘293) (or Ren et al. (WO 2022/252713 A1) (hereafter referred to as Ren ‘713) for identical reasons; see below) in view of Atmel (Atmel Corporation ARM7TDMITM (Thumb®) Datasheet).
Consider claim 1, Ren ’293 (or Ren ‘713) discloses a method for accelerating a recurrent neural network, comprising: setting MCR instructions and a CDP instruction with operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator; configuring internal registers of a recurrent neural network coprocessor through the MCR instructions; and executing an operation using one of the operators of the recurrent neural network through the CDP instruction on the basis of the configured internal registers (Ren ‘293 or Ren ‘713, claim 1, as a succinct example).
In general, Examiner submits that the aforementioned subject matter of instant claim 1 (as well as the instant drawings and instant specification, except for instant specification paragraph [0008] and a portion of instant specification paragraph [0007], which were newly added in the instant continuation-in-part application) was analogously disclosed by both Ren ‘293, which is the publication of Chinese Application No. CN 202111641429.5 (to which priority is claimed; see instant paragraph [0001] and the ADS of the instant application), and Ren ‘713, which is the publication of International Application No. PCT/CN2022/077861 (of which parent application US 17/918,572 was a national phase; see instant paragraph [0001] and the ADS of the instant application). (Examiner also notes that the specification, drawings, and claims of the immediate parent application US 17/918,572 correspond to the specification, drawings, and claims of the aforementioned Ren ‘293 and Ren ‘713.)
Examiner notes that in a continuation-in-part of an earlier U.S. application or international application, any claims in the new application not supported by the specification and claims of the parent application have an effective filing date equal to the actual filing date of the new application. In the instant case, the claimed subject matter not mentioned above (i.e., the claimed subject matter addressed below) is not supported by the specification and claims of the parent application—rather, the claimed subject matter corresponds to the aforementioned newly added instant specification paragraph 8 and portion of instant specification paragraph 7—and therefore the claim has an effective filing date equal to the actual filing date of the instant application, such that Ren ‘293 and Ren ‘713 are prior art to the claim. (Examiner notes that while a claim of Ren ‘293 and Ren ‘713 has been cited to teach the aforementioned instant limitations for succinctness, the specification and drawings of Ren ‘293 and Ren ‘713 likewise teach the aforementioned instant limitation in the same manner—i.e., with the same disclosed subject matter—as the instant specification and drawings provide support for the aforementioned instant limitation.)
However, Ren ’293 (or Ren ‘713) does not disclose that the MCR instruction is a Move to Coprocessor from arm Register instruction and the CDP instruction is a Coprocessor Data Processing instruction.
On the other hand, Atmel discloses a Move to Coprocessor from arm Register instruction (page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR)) and a Coprocessor Data Processing instruction (page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Atmel with the invention of Ren ’293 (or Ren ‘713) for increased performance for very low power consumption and price (Atmel, page 1, section: Introduction, first and second paragraph).
Consider claim 2, the overall combination entails the method according to claim 1 (see above), wherein the internal registers comprise a first register, a second register, a third register, a scale register and a control register, the MCR instructions comprise a first MCR instruction, a second MCR instruction and a third MCR instruction, and the step of configuring the internal registers of the recurrent neural network coprocessor through the MCR instructions comprises: configuring, through the first MCR instruction, a local buffer address of weight data to the first register, a local buffer address of feature data to the second register, stride block information to the scale register, and an operation mode and a write-back precision to the control register; configuring, through the second MCR instruction, a local buffer address of a first vector set to the first register, a local buffer address of a second vector set to the second register, a local buffer address of write-back information to the third register, and the stride block information to the scale register; and configuring, through the third MCR instructions, a local buffer address of input data to the first register, the local buffer address of the write-back information to the second register, and the stride block information to the scale register (Ren ‘293 or Ren ‘713, claim 2, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR)).
Consider claim 3, the overall combination entails the method according to claim 2 (see above), wherein after the step of configuring, through the first MCR instruction, the local buffer address of weight data to the first register, the local buffer address of feature data to the second register, the stride block information to the scale register, and the operation mode and the write-back precision to the control register, the method further comprises: executing an operation using the matrix multiplication operator of the recurrent neural network through the Coprocessor Data Processing instruction, partitioning a matrix of the feature data according to the stride block information, and partitioning a matrix of the weight data according to a preset weight quantity; and performing a corresponding multiply and accumulate operation on the partitioned matrix of the feature data and the partitioned matrix of the weight data according to the operation mode (Ren ‘293 or Ren ‘713, claim 3, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 4, the overall combination entails the method according to claim 2 (see above), wherein after the step of configuring, through the second MCR instruction, the local buffer address of the first vector set to the first register, the local buffer address of the second vector set to the second register, the local buffer address of write-back information to the third register, and the stride block information to the scale register, the method further comprises: executing an operation using the vector arithmetic operator of the recurrent neural network through the Coprocessor Data Processing instruction, and adding or multiplying values in the first vector set and the second vector set one by one according to the stride block information; and writing an arithmetic result back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 4, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 5, the overall combination entails the method according to claim 2 (see above), wherein after the step of configuring, through the third MCR instruction, the local buffer address of input data to the first register, the local buffer address of the write-back information to the second register, and the stride block information to the scale register, the method further comprises: executing an operation using the sigmoid activation operator of the recurrent neural network through the Coprocessor Data Processing instruction, inputting the input data into a sigmoid activation function [formula] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 5, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 6, the overall combination entails the method according to claim 2 (see above), wherein after the step of configuring, through the third MCR instruction, the local buffer address of input data to the first register, the local buffer address of the write-back information to the second register, and the stride block information to the scale register, the method further comprises: executing an operation using the tanh activation operator of the recurrent neural network through the Coprocessor Data Processing instruction, inputting the input data into a tanh activation function [formula] according to the stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 6, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 7, the overall combination entails the method according to claim 2 (see above), wherein after the step of configuring, through the third MCR instruction, the local buffer address of input data to the first register, the local buffer address of the write-back information to the second register, and the stride block information to the scale register, the method further comprises: executing an operation using the quantization operator of the recurrent neural network through the Coprocessor Data Processing instruction, and converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard in the input data into a 16-bit integer according to the stride block information, or converting a 16-bit integer in the input data into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard; and writing a conversion result back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 7, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 8, the overall combination entails the method according to claim 1 (see above), wherein the method further comprises: configuring, through a fourth MCR instruction, a main memory address to a first register, an address of a local buffer to a second register, and stride block information to a scale register; executing a data reading operation through the Coprocessor Data Processing instruction, and reading data in the main memory address into the local buffer according to the stride block information; and executing a data writing operation through the Coprocessor Data Processing instruction, and writing data in the local buffer into the main memory address according to the stride block information (Ren ‘293 or Ren ‘713, claim 8, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 9, Ren ’293 (or Ren ‘713) discloses a system for accelerating a recurrent neural network, wherein the system comprises an instruction set setting processor and an instruction set execution processor; the instruction set setting processor sets MCR instructions and a CDP instruction with operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator; the instruction set execution processor configures internal registers of a recurrent neural network coprocessor through the MCR instructions; and the instruction set execution processor executes an operation using the common basic operators of the recurrent neural network through the Coprocessor Data Processing instruction on the basis of the configured internal registers (Ren ‘293 or Ren ‘713, claim 9, as a succinct example).
In general, Examiner submits that the aforementioned subject matter of instant claim 1 (as well as the instant drawings and instant specification, except for instant specification paragraph [0008] and a portion of instant specification paragraph [0007], which were newly added in the instant continuation-in-part application) was analogously disclosed by both Ren ‘293, which is the publication of Chinese Application No. CN 202111641429.5 (to which priority is claimed; see instant paragraph [0001] and the ADS of the instant application), and Ren ‘713, which is the publication of International Application No. PCT/CN2022/077861 (of which parent application US 17/918,572 was a national phase; see instant paragraph [0001] and the ADS of the instant application). (Examiner also notes that the specification, drawings, and claims of the immediate parent application US 17/918,572 correspond to the specification, drawings, and claims of the aforementioned Ren ‘293 and Ren ‘713.)
Examiner notes that in a continuation-in-part of an earlier U.S. application or international application, any claims in the new application not supported by the specification and claims of the parent application have an effective filing date equal to the actual filing date of the new application. In the instant case, the claimed subject matter not mentioned above (i.e., the claimed subject matter addressed below) is not supported by the specification and claims of the parent application—rather, the claimed subject matter corresponds to the aforementioned newly added instant specification paragraph 8 and portion of instant specification paragraph 7—and therefore the claim has an effective filing date equal to the actual filing date of the instant application, such that Ren ‘293 and Ren ‘713 are prior art to the claim. (Examiner notes that while a claim of Ren ‘293 and Ren ‘713 has been cited to teach the aforementioned instant limitations for succinctness, the specification and drawings of Ren ‘293 and Ren ‘713 likewise teach the aforementioned instant limitation in the same manner—i.e., with the same disclosed subject matter—as the instant specification and drawings provide support for the aforementioned instant limitation.)
However, Ren ’293 (or Ren ‘713) does not disclose that the MCR instruction is a Move to Coprocessor from arm Register instruction (Examiner is interpreting the MCR acronym to correspond to “Move to Coprocessor from arm Register” in view of the analogous portion in claim 1 as well as instant specification paragraph [0008] and a portion of instant specification paragraph [0007], which were newly added in the instant continuation-in-part application) and the CDP instruction is a Coprocessor Data Processing instruction.
On the other hand, Atmel discloses a Move to Coprocessor from arm Register instruction (page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR)) and a Coprocessor Data Processing instruction (page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Atmel with the invention of Ren ’293 (or Ren ‘713) for increased performance for very low power consumption and price (Atmel, page 1, section: Introduction, first and second paragraph).
Consider claim 10, the overall combination entails a non-transitory computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the method for accelerating the recurrent neural network according to claim 1 (Ren ‘293 or Ren ‘713, claim 10, as a succinct example).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sankaralingam et al. (US 20200218965 A1) discloses accelerating a recurrent neural network including a master core distributing an input vector and weight matrix data to another processing core (see paragraph [0009]), which is relevant to the claimed accelerating a recurrent neural network, feature data, weight data, and recurrent neural network coprocessor.
Wang et al. (US 20230297375 A1) discloses provide a hardware accelerator for running an instruction set of a recurrent neural network (see paragraph [0009]). Wang also discloses a general-type computing instruction, used for performing general-type computation to implement general-type computation in the recurrent neural network, where an expression for the general-type computation is θ(w*x+b), θ represents a sigmoid activation function or tan h activation function, w represents a weight vector, x represents a data vector, and b represents a bias parameter (see paragraph [0012]). Therefore, Wang is relevant to the claimed accelerating a recurrent neural network, recurrent neural network coprocessor, sigmoid activation function, tanh activation function, and common basic operators.
Liu et al. (US 20230196068 A1) discloses accelerating a recurrent neural network (see paragraph [0008]), which is relevant to the recited accelerating a recurrent neural network.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEITH E VICARY/Primary Examiner, Art Unit 2183
Prosecution Insights