DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in this office action and presented for examination. Claims 1-9 are newly amended by the response received June 9, 2026.
Drawings
The amendment filed June 9, 2026, is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows. Applicant is required to cancel the new matter in the reply to this Office Action.
In amended FIG. 2, the “Address after stride” explanatory text is deleted, which reflects new matter.
In amended FIG. 2, the new conveyance of “Initial address” does not necessarily equate to the old conveyances of “Initial address”, and is thus new matter.
In amended FIG. 2, the new conveyance of “Weight address” does not necessarily equate to the old conveyances of “Weigh[t] address”, and is thus new matter.
In amended FIG. 2, “Result” is deleted in each cell of the rightmost table, which reflects new matter.
Amended FIG. 3 no longer depicts various matrices and associated markup, which reflects new matter.
The drawings are objected to because:
In FIG. 2 as amended, left table, it is unclear as to how two different blocks can both represent “+0x0000”.
In FIG. 2 as amended, left table, it is unclear as to how two different blocks can both represent “+0x0002”.
In FIG. 2 as amended, it is unclear as to whether each block is an initial address.
In FIG. 2 as amended, it is unclear as to whether each block is a weight address.
In FIG. 2 as amended, it is unclear as to whether the “+” in the two left tables is intended to convey a positive value or an addition with some other value.
In FIG. 2 as amended, it is unclear as to whether the “0”, “1”, and “5” in the rightmost table are actual result values, or merely convey different results by serving as labels.
Drawings shall be executed in durable, black, sufficiently dense and dark, uniformly thick and well-defined, lines and strokes without colorings. However, at least FIG. 5 does not meet this requirement.
The height of the numbers and letters shall not be less than 0.32 cm. However, the figures do not meet this requirement.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 2-7 are objected to because of the following informalities. Appropriate correction is required.
Claim 2 recites “register,-a” in line 11. Regardless of whether the horizontal line preceding “a” is a hyphen or a strikethrough mark, this language should read “register, a” for grammatical clarity.
Claims 3-7 are objected to for failing to alleviate the objection of claim 2 above.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “configuring Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction to correspond to operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator” in lines 2-6. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0007]) does not appear to provide support for “configuring” Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction “to correspond to” “operators” of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator.
Claims 2-8 and 10 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 9 recites the limitation “the instruction set setting processor configures Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction to correspond to operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator” in lines 3-7. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [00016]) does not appear to provide support for an instruction set setting processor that “configures” Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction “to correspond to” “operators” of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “configuring Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction to correspond to operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator” in lines 2-6. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means to “configur[e]” Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction “to correspond to” “operators” of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator.
Claims 2-8 and 10 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 2 recites the limitation “the third MCR instructions” in line 14. However, there is insufficient antecedent basis for this limitation in the claims.
Claims 3-7 are rejected for failing to alleviate the rejections of claim 2 above.
Claim 8 recites the limitation “executing a data reading operation through the CDP instruction, and reading data in the main memory address into the local buffer according to the stride block information” in lines 5-7. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing a data reading operation through the CDP instruction” is the same as, or distinct from, “reading data in the main memory address into the local buffer according to the stride block information”.
Claim 8 recites the limitation “executing a data writing operation through the CDP instruction, and writing data in the local buffer into the main memory address according to the stride block information” in lines 8-10. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether “executing a data writing operation through the CDP instruction” is the same as, or distinct from, “writing data in the local buffer into the main memory address according to the stride block information”.
Claim 9 recites the limitation “the instruction set setting processor configures Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction to correspond to operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator” in lines 3-7. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means to “configure[]” Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction “to correspond to” “operators” of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator.
Claim 9 recites the limitation “executes an operation using the operators of the recurrent neural network through the CDP instruction on the basis of the configured internal registers” in lines 10-12. However, it is indefinite as to whether the recited [single] operation uses [all of] the operators (e.g., a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator, and a quantization operator), or another interpretation is intended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ren et al. (CN 114298293 A) (hereafter referred to Ren ‘293) (or Ren et al. (WO 2022/252713 A1) (hereafter referred to as Ren ‘713) for identical reasons; see below) in view of Atmel (Atmel Corporation ARM7TDMITM (Thumb®) Datasheet).
Consider claim 1, Ren ’293 (or Ren ‘713) discloses a method for accelerating a recurrent neural network, comprising: configuring MCR instructions and a CDP instruction to correspond to operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator; configuring internal registers of a recurrent neural network coprocessor through the MCR instructions; and executing an operation using one of the operators of the recurrent neural network through the CDP instruction on the basis of the configured internal registers (Ren ‘293 or Ren ‘713, claim 1, as a succinct example).
In general, Examiner submits that the aforementioned subject matter of instant claim 1 (as well as the instant drawings and instant specification, except for instant specification paragraph [0008] and a portion of instant specification paragraph [0007], which were newly added in the instant continuation-in-part application) was analogously disclosed by both Ren ‘293, which is the publication of Chinese Application No. CN 202111641429.5 (to which priority is claimed; see instant paragraph [0001] and the ADS of the instant application), and Ren ‘713, which is the publication of International Application No. PCT/CN2022/077861 (of which parent application US 17/918,572 was a national phase; see instant paragraph [0001] and the ADS of the instant application). (Examiner also notes that the specification, drawings, and claims of the immediate parent application US 17/918,572 correspond to the specification, drawings, and claims of the aforementioned Ren ‘293 and Ren ‘713.)
Examiner notes that in a continuation-in-part of an earlier U.S. application or international application, any claims in the new application not supported by the specification and claims of the parent application have an effective filing date equal to the actual filing date of the new application. In the instant case, the claimed subject matter not mentioned above (i.e., the claimed subject matter addressed below) is not supported by the specification and claims of the parent application—rather, the claimed subject matter corresponds to the aforementioned newly added instant specification paragraph 8 and portion of instant specification paragraph 7—and therefore the claim has an effective filing date equal to the actual filing date of the instant application, such that Ren ‘293 and Ren ‘713 are prior art to the claim. (Examiner notes that while a claim of Ren ‘293 and Ren ‘713 has been cited to teach the aforementioned instant limitations for succinctness, the specification and drawings of Ren ‘293 and Ren ‘713 likewise teach the aforementioned instant limitation in the same manner—i.e., with the same disclosed subject matter—as the instant specification and drawings provide support for the aforementioned instant limitation.)
However, Ren ’293 (or Ren ‘713) does not disclose that the MCR instruction is a Move to Coprocessor from arm Register instruction and the CDP instruction is a Coprocessor Data Processing instruction.
On the other hand, Atmel discloses a Move to Coprocessor from arm Register instruction (page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR)) and a Coprocessor Data Processing instruction (page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Atmel with the invention of Ren ’293 (or Ren ‘713) for increased performance for very low power consumption and price (Atmel, page 1, section: Introduction, first and second paragraph).
Consider claim 2, the overall combination entails the method according to claim 1 (see above), wherein the internal registers comprise a first register, a second register, a third register, a scale register and a control register, the MCR instructions comprise a first MCR instruction, a second MCR instruction and a third MCR instruction, and the step of configuring the internal registers of the recurrent neural network coprocessor through the MCR instructions comprises: configuring, through the first MCR instruction, a local buffer address of weight data to the first register, a local buffer address of feature data to the second register, first stride block information to the scale register, and an operation mode and a write-back precision to the control register; configuring, through the second MCR instruction, a local buffer address of a first vector set to the first register, a local buffer address of a second vector set to the second register, a local buffer address of write-back information to the third register, and second stride block information to the scale register; and configuring, through the third MCR instructions, a local buffer address of input data to the first register, the local buffer address of the write-back information to the second register, and third stride block information to the scale register (Ren ‘293 or Ren ‘713, claim 2, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR)).
Consider claim 3, the overall combination entails the method according to claim 2 (see above), wherein the executed operation uses the matrix multiplication operator of the recurrent neural network by partitioning a matrix of the feature data according to the first stride block information, and partitioning a matrix of the weight data according to a preset weight quantity; and performing a corresponding multiply and accumulate operation on the partitioned matrix of the feature data and the partitioned matrix of the weight data according to the operation mode (Ren ‘293 or Ren ‘713, claim 3, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 4, the overall combination entails the method according to claim 2 (see above), wherein the executed operation uses the vector arithmetic operator of the recurrent neural network by adding or multiplying values in the first vector set and the second vector set one by one according to the second stride block information; and writing an arithmetic result back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 4, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 5, the overall combination entails the method according to claim 2 (see above), wherein the executed operation uses the sigmoid activation operator of the recurrent neural network by inputting the input data into a sigmoid activation function [formula] according to the third stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 5, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 6, the overall combination entails the method according to claim 2 (see above), wherein the executed operation uses the tanh activation operator of the recurrent neural network by inputting the input data into a tanh activation function [formula] according to the third stride block information, and returning a result value; and writing the result value back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 6, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 7, the overall combination entails the method according to claim 2 (see above), wherein the executed operation uses the quantization operator of the recurrent neural network by converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard in the input data into a 16-bit integer according to the third stride block information, or converting a 16-bit integer in the input data into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard; and writing a conversion result back to a local buffer according to the write-back information (Ren ‘293 or Ren ‘713, claim 7, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 8, the overall combination entails the method according to claim 1 (see above), wherein the method further comprises: configuring, through a fourth MCR instruction, a main memory address to a first register, an address of a local buffer to a second register, and stride block information to a scale register; executing a data reading operation through the CDP instruction, and reading data in the main memory address into the local buffer according to the stride block information; and executing a data writing operation through the CDP instruction, and writing data in the local buffer into the main memory address according to the stride block information (Ren ‘293 or Ren ‘713, claim 8, as a succinct example; Atmel, page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR); page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
Consider claim 9, Ren ’293 (or Ren ‘713) discloses a system for accelerating a recurrent neural network, wherein the system comprises an instruction set setting processor and an instruction set execution processor; the instruction set setting processor configures MCR instructions and a CDP instruction to correspond to operators of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator; the instruction set execution processor configures internal registers of a recurrent neural network coprocessor through the MCR instructions; and the instruction set execution processor executes an operation using the operators of the recurrent neural network through the CDP instruction on the basis of the configured internal registers (Ren ‘293 or Ren ‘713, claim 9, as a succinct example).
In general, Examiner submits that the aforementioned subject matter of instant claim 1 (as well as the instant drawings and instant specification, except for instant specification paragraph [0008] and a portion of instant specification paragraph [0007], which were newly added in the instant continuation-in-part application) was analogously disclosed by both Ren ‘293, which is the publication of Chinese Application No. CN 202111641429.5 (to which priority is claimed; see instant paragraph [0001] and the ADS of the instant application), and Ren ‘713, which is the publication of International Application No. PCT/CN2022/077861 (of which parent application US 17/918,572 was a national phase; see instant paragraph [0001] and the ADS of the instant application). (Examiner also notes that the specification, drawings, and claims of the immediate parent application US 17/918,572 correspond to the specification, drawings, and claims of the aforementioned Ren ‘293 and Ren ‘713.)
Examiner notes that in a continuation-in-part of an earlier U.S. application or international application, any claims in the new application not supported by the specification and claims of the parent application have an effective filing date equal to the actual filing date of the new application. In the instant case, the claimed subject matter not mentioned above (i.e., the claimed subject matter addressed below) is not supported by the specification and claims of the parent application—rather, the claimed subject matter corresponds to the aforementioned newly added instant specification paragraph 8 and portion of instant specification paragraph 7—and therefore the claim has an effective filing date equal to the actual filing date of the instant application, such that Ren ‘293 and Ren ‘713 are prior art to the claim. (Examiner notes that while a claim of Ren ‘293 and Ren ‘713 has been cited to teach the aforementioned instant limitations for succinctness, the specification and drawings of Ren ‘293 and Ren ‘713 likewise teach the aforementioned instant limitation in the same manner—i.e., with the same disclosed subject matter—as the instant specification and drawings provide support for the aforementioned instant limitation.)
However, Ren ’293 (or Ren ‘713) does not disclose that the MCR instruction is a Move to Coprocessor from arm Register instruction (Examiner is interpreting the MCR acronym to correspond to “Move to Coprocessor from arm Register” in view of the analogous portion in claim 1 as well as instant specification paragraph [0008] and a portion of instant specification paragraph [0007], which were newly added in the instant continuation-in-part application) and the CDP instruction is a Coprocessor Data Processing instruction.
On the other hand, Atmel discloses a Move to Coprocessor from arm Register instruction (page 70, MCR; ARM source/destination register; A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR)) and a Coprocessor Data Processing instruction (page 66, Coprocessor Data Operations (CDP); This class of instruction is used to tell a coprocessor to perform some internal operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Atmel with the invention of Ren ’293 (or Ren ‘713) for increased performance for very low power consumption and price (Atmel, page 1, section: Introduction, first and second paragraph).
Consider claim 10, the overall combination entails a non-transitory computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the method for accelerating the recurrent neural network according to claim 1 (Ren ‘293 or Ren ‘713, claim 10, as a succinct example).
Response to Arguments
Applicant on page 1 of the remarks (page 8 of the overall response) argues: “The Examiner objected to the Specification for containing typographical and formatting errors in paragraphs [00012], [00030], and [00048] . Applicant has amended the Specification to correct these informalities.”
In view of the aforementioned amendments to the specification, the previously presented objections to the specification are withdrawn.
Applicant on page 1 of the remarks argues: ‘The Examiner objected to the drawings for various informalities, including clarity of lines/strokes, text height, overlapping text, and spelling errors ("weigh" and "interfce") . Applicant submits herewith Replacement Sheets correcting all identified informalities in compliance with 37 CFR 1.121(d). The objection to the drawings should therefore be overcome.’
Various previously presented objections to the drawings are withdrawn in the view of the amendments to the drawings. However, various previously presented objections to the drawings remain applicable. In addition, the amendments to the drawings catalyze further objections and instances of new matter; see the Drawings section above.
Applicant on page 1 of the remarks argues: ‘The Examiner indicated that "setting" MCR and CDP instructions "with operators" in Claims 1 and 9 was indefinite . Applicant has amended the claims to read "configuring MCR instructions and a CDP instruction to correspond to operators," which clarifies the relationship between the instructions and the operators.’
However, it is indefinite as to what it means to “configur[e]” Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction “to correspond to” “operators” of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator.
Applicant on page 1 of the remarks argues: ‘The Examiner indicated that Claim 2 repeatedly recited configuring stride block information, raising ambiguity . Applicant has amended Claim 2 to specify configuring "first stride block information," "second stride block information," and "third stride block information" through the first, second, and third MCR instructions, respectively, clearly resolving the overlap.’
In view of the aforementioned amendments, the associated previously presented indefinite rejection is withdrawn.
Applicant on page 1 of the remarks argues: ‘In addition, the antecedent basis issue regarding "the third MCR instructions" has been corrected to "the third MCR instruction".’
However, the claims received June 9, 2026, do not appear to reflect such a correction.
Applicant across pages 1-2 of the remarks argues: ‘Regarding Claims 3-7, the Examiner indicated it was unclear whether the "executing an operation" step was the same as, or distinct from, the "executing an operation" step in Claim 1 . Applicant has amended the dependent claims to recite "the executed operation uses [the respective operator]... by [performing the respective data processing step]". This expressly ties the operation in the dependent claims to the single operation step recited in Claim 1, removing the ambiguity.’
In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn.
Applicant on page 2 of the remarks argues: ‘Regarding Claim 9, the Examiner objected to the phrase "common basic operators" as lacking antecedent basis and relying on unclear criteria for "common" and "basic" . Applicant has removed the terms "common basic" from Claim 9, resolving the issue.’
In view of the aforementioned amendment, the associated previously presented indefinite rejection is withdrawn.
Applicant on page 3 of the remarks argues: ‘It is a well-established tenet of patent law that explicitly stating the inherent, well-known meaning of a standard term or acronym does not constitute new matter. As the Examiner's own cited reference (Atmel ARM7TDMI Datasheet) clearly demonstrates, "MCR" and "CDP" are industry-standard instructions in the ARM architecture that specifically and universally stand for "Move to Coprocessor from arm Register" and "Coprocessor Data Processing," respectively. A POSITA reading the parent applications—which explicitly discuss Cortex-M, ARM architecture, and coprocessor instructions—would immediately and necessarily understand the acronyms MCR and CDP to mean exactly these phrases. Adding the spelled-out names of these standard ARM instructions merely clarifies terms that were already inherently disclosed and fully possessed by the inventors at the time of the parent filing. Therefore, spelling out these acronyms does not introduce new matter. The claims remain fully supported by the specification of the parent applications (Ren '293 and Ren '713) and are rightfully entitled to their priority date of December 29, 2021.’
However, Examiner maintains that disclosure of the acronyms MCR and CDP do not inherently provide support for "Move to Coprocessor from arm Register" and "Coprocessor Data Processing”. Examiner notes that Applicant’s response received August 7, 2024, in the parent application 17/918572 contained amendments to replace “MCR” with “Master Control Reset”, which reflects the possibility that an acronym can have multiple meanings. Examiner notes that Cortex-M does not appear to be disclosed in the Atmel ARM7TDMI Datasheet. Examiner also notes that Applicant, in the parent application, argued that “based on the Cortex-M processor” was “a meaningless limitation” (see page 24 and 30 of the response dated August 7, 2024), which reflects the acronyms not necessarily having a particular meaning merely because the instant application discloses Cortex-M.
Examiner notes that the instant application is a continuation-in-part, which reflects the reasonable position that the acronyms MCR and CDP do not inherently provide support for "Move to Coprocessor from arm Register" and "Coprocessor Data Processing”. Examiner further notes that a limitation should be interpreted in light of the specification, and the newly added subject matter in the continuation-in-part goes beyond spelling out the acronyms MCR and CDP, thereby further affecting interpretation of the claimed subject matter. For example, paragraph [0008] in the instant continuation-in-part application appears to be newly added relative to the parent applications and discloses “Recurrent neural network coprocessor configures its internal registers through MCR (Move to Coprocessor from arm Register) instructions, and reads its internal registers through the MRC (Move to arm Register from Coprocessor) instruction. A MCR instruction is one of the coprocessor instructions of ARM Company, which is used to transfer data from the general register of ARM processor to the register of coprocessor. This is a write operation, which is usually used to set the state of the coprocessor or configure its control register. A MRC instruction is used to transfer data from coprocessor to general register of ARM core processor. This instruction is usually used to read the state of the coprocessor or the value of its internal register. Recurrent neural network coprocessor starts the corresponding artificial intelligence operation through a CDP (Coprocessor Data Processing) instruction, which is also one of ARM coprocessor instructions and is used to instruct the coprocessor to perform data processing operations.” Therefore, for example, in the instant continuation-in-part application, unlike the parent application, “MCR” must be interpreted in light of the new subject matter that a MCR instruction is used to transfer data from the “general” register and is “usually” used to “set the state of the coprocessor”. For all of the above reasons, Examiner submits that the priority date of the claims is the filing date of the instant continuation-in-part application.
Examiner generally notes, for the purposes of compact prosecution, that if Applicant is arguing that the recited Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction are well-known, it is unclear as to what the inventive concept of the independent claims are, given that recurrent neural networks, matrix multiplication, vector arithmetic, and so forth, are likewise well-known. To the extent that the inventive concept is particularly “configuring” Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction “to correspond to” “operators” of the recurrent neural network, wherein the operators comprise a matrix multiplication operator, a vector arithmetic operator, a sigmoid activation operator, a tanh activation operator and a quantization operator, Examiner notes that the aforementioned limitation is indefinite (see above) and consequently unclear as to how the limitation might reflect behavior that goes beyond well-known use of Move to Coprocessor from arm Register (MCR) instructions and a Coprocessor Data Processing (CDP) instruction to perform a well-known data processing operation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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