DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/05/2026 and 10/31/2024 have been considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-12 and 14-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ohba et al. (US 20060284671; hereinafter Ohba).
Regarding claim 1, Ohba discloses in figure(s) 1-13 An apparatus (41, 43 fig. 11) comprising:
a driver (41; fig. 11) configured to receive an input signal, the input signal comprising a first signal component (in_a) and a second signal component (in_b), the first signal component being characterized by a first voltage level and a first polarity, the second signal component being characterized by a second voltage level and a second polarity, the first polarity being opposite the second polarity (filter C1 and C2, and
"the amplifying unit is a differential amplifier circuit for outputting a differential
output signal of a transistor differential pair”, clm 4);
a first circuit (43, R7, R8) coupled to the driver, the first circuit being configured to adjust a first voltage level by applying a first bias voltage (@R7) to the first signal component and adjust a second voltage level by applying a second bias voltage (@R8) to the second signal component (clm. 21 - input offset component is corrected by adding a correction voltage to an input bias voltage of the differential amplifier circuit); and
a quantizer (211) coupled to the driver, the quantizer being configured to generate an output signal based at least on the first voltage level and the second voltage level.
Regarding claim 6, Ohba discloses in figure(s) 1-13 the apparatus of claim 1, wherein the quantizer comprises a sampling circuit configured to sample the input signal based on a predetermined interval (SW4, SW5; fig. 11).
Regarding claim 7, Ohba discloses in figure(s) 1-13 the apparatus of claim 1, wherein the first circuit comprises a second circuit (132; fig. 11 ) configured to receive a first reference voltage and generate the first bias voltage based on the first reference voltage.
Regarding claim 8, Ohba discloses in figure(s) 1-13 the apparatus of claim 7, wherein the first circuit comprises a third circuit configured to receive a second reference voltage and generate the second bias voltage based on the second reference voltage (332; fig. 11).
Regarding claim 10, Ohba discloses in figure(s) 1-13 the apparatus of claim 1, wherein the output signal comprises a digital signal (para. 76 - A correction control unit 431 receives a comparison result from the comparator 211 to adjust output signals of the DACs 132 and 142, 332, 333, 432, and 433).
Regarding claim 11, Ohba discloses in figure(s) 1-13 the apparatus of claim 1, wherein the first bias voltage is configured to increase the first voltage level and the second bias voltage is configured to decrease the second voltage level (para. 63 – “if the DC offset indicated by the output of the comparator 211 is a negative value, the U/D counter 234 is incremented; otherwise, the counter is decremented. The count value of the U/0 counter 234 is passed through the !atcl1/througl1 circuit 235 and input to the DAC 132” – implies both bias levels can be increased and decreased).
Regarding claim 12, Ohba discloses in figure(s) 1-13 An apparatus (41, 43 fig. 11) comprising:
a driver (41; fig. 11) configured to receive an input signal, the input signal comprising a first signal component (in_a) and a second signal component (in_b), the first signal component being characterized by a first voltage level, the second signal component being characterized by a second voltage level (clm. 4 - the amplifying unit is a differential amplifier circuit for outputting a differential output signal of a transistor differential pair);
a first circuit (43, R7, R8) coupled to the driver, the first circuit being configured to adjust a first voltage level by applying a first bias voltage (@R7) to the first signal component and adjust a second voltage level (@R8) by applying a second bias voltage to the second signal component (clm. 21 - input offset component is corrected by adding a correction voltage to an input bias voltage of the differential amplifier circuit); and
a quantizer (211) coupled to the driver, the quantizer being configured to generate an output signal based at least on the first voltage level and the second voltage level.
Regarding claim 14, Ohba discloses in figure(s) 1-13 the apparatus of claim 12, wherein the first bias voltage is configured to increase the first voltage level (para. 63 – “if the DC offset indicated by the output of the comparator 211 is a negative value, the U/D counter 234 is incremented; otherwise, the counter is decremented. The count value of the U/0 counter 234 is passed through the !atcl1/througl1 circuit 235 and input to the DAC 132” – implies both bias levels can be increased and decreased).
Regarding claim 15, Ohba discloses in figure(s) 1-13 the apparatus of claim 12, wherein the second bias voltage is configured to decrease the second voltage level (para. 63 – “if the DC offset indicated by the output of the comparator 211 is a negative value, the U/D counter 234 is incremented; otherwise, the counter is decremented. The count value of the U/0 counter 234 is passed through the !atcl1/througl1 circuit 235 and input to the DAC 132” – implies both bias levels can be increased and decreased).
Regarding claim(s) 5 and 16, Ohba discloses in figure(s) 1-13 the apparatus of claim 1 and claim 12, respectively, wherein the first circuit is coupled to the driver through a first node and a second node, the first node is associated with the first signal component, and the second node is associated with the second signal component (nodes connected to upper terminals of R7 and R8; fig. 11).
Regarding claim 18, Ohba discloses in figure(s) 1-13 An apparatus (41, 43 fig. 11) comprising:
a driver (41; fig. 11) configured to receive an input signal, the input signal comprising a first signal component (in_a) and a second signal component (in_b), the first signal component being characterized by a first voltage level, the second signal component being characterized by a second voltage level (clm. 4 - the amplifying unit is a differential amplifier circuit for outputting a differential output signal of a transistor differential pair);
a first circuit (43, R7, R8) coupled to the driver, the first circuit comprising a second circuit configured to generate a first bias voltage (@R7) and a third circuit configured to generate a second bias voltage (@R8), the first circuit being configured to adjust the first voltage level by applying the first bias voltage to the first signal component and adjust the second voltage level by applying the second bias voltage to the second signal component (clm. 21 - input offset component is corrected by adding a correction voltage to an input bias voltage of the differential amplifier circuit); and
a quantizer (211) coupled to the driver, the quantizer being configured to generate an output signal based at least on the first voltage level and the second voltage level.
Regarding claim 19, Ohba discloses in figure(s) 1-13 the apparatus of claim 18, further comprising a controller coupled to the first circuit, the controller being configured to adjust the first bias voltage and the second bias voltage based at least on the output signal (para. 79 - the comparator 211 may function to
correct an input offset, and the offset may be corrected based on an input
voltage of the comparator 211 to therby minimize a detection error of the
comparator 211. Hence, the correction control units 231, 331 and 431 can
precisely determine whether or not the DC offset is converged).
Regarding claim(s) 9, 17 and 20, Ohba discloses in figure(s) 1-13 the apparatus of claim 1, claim 12 and claim 18, respectively, wherein the output signal is associated with a difference between the first voltage level and the second voltage level (para. 59 - a comparator 211 determines a potential difference between the output terminals out_a and out_b of the amplifying unit 21).
Claim(s) 1-4 and 12-13 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Masenas et al. (US 20030063020; hereinafter Masenas).
Regarding claim 1, Masenas discloses in figure(s) 1-4 An apparatus (fig. 3) comprising:
a driver (30,55,75; fig. 3) configured to receive an input signal (Vinp, Vinm), the input signal comprising a first signal component (Vinp) and a second signal component (Vinm), the first signal component being characterized by a first voltage level and a first polarity, the second signal component being characterized by a second voltage level and a second polarity, the first polarity being opposite the second polarity (para. 14 - The input voltage signal comprises a plurality of differential analog input signals);
a first circuit (10,14,85,80,90,20; fig. 3) coupled to the driver, the first circuit being configured to adjust a first voltage level by applying a first bias voltage (upper node of top component 80) to the first signal component and adjust a second voltage level by applying a second bias voltage (lower node of bottom component 80) to the second signal component; and
a quantizer (105,45; fig. 3) coupled to the driver, the quantizer being configured to generate an output signal (115) based at least on the first voltage level and the second voltage level.
Regarding claim 12, Masenas discloses in figure(s) 1-4 An apparatus (fig. 3) comprising:
a driver (30,55,75; fig. 3) configured to receive an input signal (Vinp, Vinm), the input signal comprising a first signal component (Vinp) and a second signal component (Vinm), the first signal component being characterized by a first voltage level, the second signal component being characterized by a second voltage level (para. 14 - The input voltage signal comprises a plurality of differential analog input signals);
a first circuit (10,14,85,80,90,20; fig. 3) coupled to the driver, the first circuit being configured to adjust a first voltage level by applying a first bias voltage (upper node of top component 80) to the first signal component and adjust a second voltage level by applying a second bias voltage (lower node of bottom component 80) to the second signal component; and
a quantizer (105,45; fig. 3) coupled to the driver, the quantizer being configured to generate an output signal (115) based at least on the first voltage level and the second voltage level.
Regarding claim(s) 2 and 13, Masenas discloses in figure(s) 1-4 the apparatus of claim 1 and claim 12, respectively, further comprising a controller coupled to the first circuit, the controller being configured to adjust the first bias voltage and the second bias voltage based at least on the output signal (para. 48 - During the dynamic calibration procedure, then bits 115 that are the digital result of the ADC are produced in the same way as during normal operation, and are coupled as input to the Calibration Engine 20. These n bits 115 constitute the feedback that is used to determine the set of outputs generated by Calibration Engine 20).
Regarding claim 3, Masenas discloses in figure(s) 1-4 the apparatus of claim 2, wherein the controller is configured to store a plurality of bias voltage profiles comprising the first bias voltage and the second bias voltage (para. 33 - The calibration results which are the final settings for the gain, offset, and reference adjust signals are stored in registers or memory cells on the chip).
Regarding claim 4, Masenas discloses in figure(s) 1-4 the apparatus of claim 1, wherein the first circuit is further configured to calibrate the first bias voltage and the second bias voltage based on a reference signal (fig. 3).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chern et al. (US 7528752) discloses “Offset Compensation Scheme Using A DAC”.
Xu et al. (US 8400337) discloses “Offset Cancellation By Biasing The Body Of A Transistor”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
Prosecution Insights