Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is responsive to the U.S. Patent Application Ser. No 18/934,000 filed 10/31/2024 to 02/20/2025.
Gerneral Remarks
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 11.
b. Claims 1-20 are pending on the application.
Drawings
3. The drawings were received on 10/31/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 01/31/2025. The information disclosed therein was considered.
Specification
4. The disclosure is objected to because of the following informalities:
In the first paragraph of the specification, the status of the parent application No. 18/221,330 should be updated; namely, it has matured into U.S. Patent No. 12,159,669. Appropriate correction is required.
Double Patenting
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
6. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12,159,669 in view of Salters et al (Pub. No.: US 2011/0205787 A1).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1 and 11 of US patent 12,159,669 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-10 and 12-20.
Application: 18/934,000.
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Patent No.: US 12,159,669.
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Application: 18/934,000.
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Patent No.: US 12,159,669.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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7. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11,742,022 in view of Salters et al (Pub. No.: US 2011/0205787 A1).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1 and 11 of US patent 11,742,022 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-10 and 12-20.
Application: 18/934,000.
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Patent No.: US 11,742,022.
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Application: 18/934,000.
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Patent No.: US 11,742,022.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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8. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-28 of U.S. Patent No. 11,211,125 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1, 11 and 20 of US patent 11,211,125 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-10, 12-19 and 21-28.
Application: 18/934,000.
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Patent No.: US 11,211,125.
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Application: 18/934,000.
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Patent No.: US 11,211,125.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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9. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 10,861,548 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1 and 11 of US patent 10,861,548 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-10 and 12-20.
Application: 18/934,000.
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Patent No.: US 10,861,548.
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Application: 18/934,000.
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Patent No.: US 10,861,548.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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10. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 10,529,424 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1 and 11 of US patent 10,529,424 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-10 and 12-20.
Application: 18/934,000.
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Patent No.: US 10,529,424.
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Application: 18/934,000.
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Patent No.: US 10,529,424.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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11. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 10,249,368 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1 and 11 of US patent 10,249,368 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-10 and 12-20.
Application: 18/934,000.
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Patent No.: US 10,249,368.
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Application: 18/934,000.
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Patent No.: US 10,249,368.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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12. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-18 of U.S. Patent No. 9,922,711 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1 and 10 of US patent 9,922,711 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-9 and 11-18.
Application: 18/934,000.
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Patent No.: US 9,922,711.
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Application: 18/934,000.
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Patent No.: US 9,922,711.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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13. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-17 of U.S. Patent No. 9,666,275 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1, 9 and 14 of US patent 9,666,275 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-8, 10-13 and 15-17.
Application: 18/934,000.
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Patent No.: US 9,666,275.
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Application: 18/934,000.
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Patent No.: US 9,666,275.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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14. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 9,401,206 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1, 10 and 15 of US patent 9,401,206 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-9, 11-14 and 16-20.
Application: 18/934,000.
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Patent No.: US 9,401,206.
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Application: 18/934,000.
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Patent No.: US 9,401,206.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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15. Claims 1-20 of the instant application is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 9,025,358 in view of Choi (US. 11,429,307).
All of the limitation of pending claims 1 and 11 can be found in conflicting claims 1, 16 and 17 of US patent 9,025,358 with the exception of the additional limitation of “a volatile memory having at least two stable configured to store data when power is applied to the memory cell”.
Salters et al discloses a volatile memory device 1 (see Figure 1) includes a memory cell 2 of the memory retain their data as long as power to the cell remain applied and contain at least two stable starts: one stable state can be used tp represent and so store a logical “0” and the other stable state can be used to represent a logical “1” (see paragraph 0008, an sram is a type of volalile memory….This distable latching circuit…tow stable states…logical “1”). It would have been obvious to include the volatile memory, disclosed by Salter et al in a memory device, as instantly claimed to enable the “tow stable states” function as instantly claimed, thus providing the advantage of retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not power any more.
Claims 2-10 and 12-20 are therefore rejected under Patent in view of Salters et al for the same as claims 2-15 and 18-20.
Application: 18/934,000.
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Patent No.: US 9,025,358.
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Application: 18/934,000.
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Patent No.: US 9,025,358.
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Salters et al (Pub. No.: US. 2011/0205787 A1).
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Allowable Subject Matter
16. Claims 1-20 are presently rejected under obviousness double patenting, but would be allowable provided that a terminal disclaimer is filed.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tessariol et al (US. 9,711,223 B2) discloses apparatus and method including a bipolar junction transistor coupled to a string of memory cells.
Ong (US. 2012/0020159 A1) discloses nonvolatile static ram cell circuit and timing method.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824
571-272-1876
Miner.luu@uspto.gov
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