DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/31/2024 have been considered by the Examiner.
Claim Objections
Claim(s) 8 and 18 are objected to because of the following informalities:
Claim(s) 8 and 18 recite a term “conductive pads”. Examiner suggests amending the term to recite “the conductive pads” to restore clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11 and 14-18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Khandros et al. (US 5900738; hereinafter Khandros).
Regarding claim 1, Khandros discloses in figure(s) 1-38 An IC testing apparatus, comprising:
a printed circuit board (pc board 442; fig. 27) including a test circuit (semiconductor device 452; col. 4 lines 25-30 :- a production, test or burn-in socket for a semiconductor package or semiconductor device);
a plurality of conductive pads (pads 443,444) located on an upper surface of the printed circuit board (442) and electrically connected to the test circuit (452); and
a plurality of elastic conductive pillars (resilient contacts 446) directly integrated onto the conductive pads of the printed circuit board (col. 18 lines 1-10, col. 22 lines 10-15 - Contact structures 446 are mounted on the pads 443 and are comprised of a skeleton 447 and shell 448 construction in the manner shown to provide a resilient contact structure… integrated resilient contacts).
Regarding claim 2, Khandros discloses in figure(s) 1-38 the IC testing apparatus of claim 1, further comprising an isolation layer surrounding the elastic conductive pillars (col. 11 lines 10-15 :- layer 229 is covered with another isolation layer 231 of a nickel alloy which is covered with a gold layer 232; fig. 15).
Regarding claim 3, Khandros discloses in figure(s) 1-38 the IC testing apparatus of claim 2, wherein the distance between the isolation layer (231; fig. 15) and the elastic conductive pillars (236) is greater than 0.
Regarding claim 4, Khandros discloses in figure(s) 1-38 the IC testing apparatus of claim 1, wherein the elastic conductive pillars have a plurality of different cross-sectional shapes (different cross-sections of contact pillars in figs. 1-5).
Regarding claim 5, Khandros discloses in figure(s) 1-38 the IC testing apparatus of claim 1, wherein the material of the isolation layer is selected from the group consisting of polyamide (321,322; col. 12 lines 67; fig. 20), PCB materials, silicone, and ceramics.
Regarding claim 6, Khandros discloses in figure(s) 1-38 the IC testing apparatus of claim 1, wherein a plurality of conductive particles is embedded within the elastic conductive pillars (446) and the conductive particles are selected from the group consisting of metal powders, metal alloy powders, graphite powders, conductive compounds, and conductive plastics (col. 2 lines 15-20 :- electrically conducting filled compliant elastomeric layer).
Regarding claim 7, Khandros discloses in figure(s) 1-38 the IC testing apparatus of claim 2, wherein the height of the isolation layer (231; fig. 15) is approximately 0.2 to 4 times the height of the elastic conductive pillars (228).
Regarding claim 8, Khandros discloses in figure(s) 1-38 the IC testing apparatus of claim 1, wherein the elastic conductive pillars (446; fig. 27) are laterally connected to conductive pads (443,444) which supply the same electrical potential (col. 18 lines 1-5 - “Contact structures 446 are mounted on the pads 443 and are comprised of a skeleton 447 and shell 448 construction” implies same potential).
Regarding claim 9, Khandros discloses in figure(s) 1-38 a method of manufacturing an IC testing apparatus, comprising the steps of:
providing a printed circuit board(pc board 442; fig. 27) including a test circuit (semiconductor device 452; col. 4 lines 25-30 :- a production, test or burn-in socket for a semiconductor package or semiconductor device);
forming a plurality of conductive pads (pads 443,444) electrically connected to the test circuit (452) on an upper surface of the printed circuit board (442); and
forming a plurality of elastic conductive pillars (resilient contacts 446) on the conductive pads (col. 18 lines 1-10, col. 22 lines 10-15 - Contact structures 446 are mounted on the pads 443 and are comprised of a skeleton 447 and shell 448 construction in the manner shown to provide a resilient contact structure… integrated resilient contacts).
Regarding claim 10, Khandros discloses in figure(s) 1-38 the method of claim 9, wherein the step of forming the elastic conductive pillars on the conductive pads comprises: forming a sacrificial layer on the printed circuit board; forming a plurality of patterned spaces on the sacrificial layer to expose the conductive pads; filling conductive gel into the patterned spaces and curing the conductive gel; and removing the sacrificial layer (col. 9 lines 30-50 :- flexible elongate element 187 … by suitable means such as a wedge bond to a sacrificial metal layer 188 as for example an aluminum layer which is secured to the component 102 by a thick photoresist 189 which serves as a standoff. After that step has been completed, the aluminum layer 188 can be sacrificed by etching it away with a suitable etch such as sodium hydroxide. The flexible elongate element 187 can then be coated in the manner hereinbefore described with a shell 190 formed of a nickel cobalt alloy or other suitable material as hereinbefore described to provide a free standing spring-like contact structure 186; fig. 11).
Regarding claim 11, Khandros discloses in figure(s) 1-38 the method of claim 9, further comprising forming an isolation layer on the printed circuit board, the isolation layer surrounding the elastic conductive pillars (col. 11 lines 10-15 :- layer 229 is covered with another isolation layer 231 of a nickel alloy which is covered with a gold layer 232; fig. 15).
Regarding claim 14, Khandros discloses in figure(s) 1-38 the method of claim 11, wherein the height of the isolation layer (231; fig. 15) is approximately 0.2 to 4 times the height of the elastic conductive pillars (228).
Regarding claim 15, Khandros discloses in figure(s) 1-38 the method of claim11, wherein the distance between the isolation layer (231; fig. 15) and the elastic conductive pillars (236) is greater than 0.
Regarding claim 16, Khandros discloses in figure(s) 1-38 the method of claim 11, wherein the material of the isolation layer is selected from the group consisting of polyamide (321,322; col. 12 lines 67; fig. 20), PCB materials, silicone, and ceramics.
Regarding claim 17, Khandros discloses in figure(s) 1-38 the method of claim 10, wherein a plurality of conductive particles is embedded within the elastic conductive pillars (446) and the conductive particles are selected from the group consisting of metal powders, metal alloy powders, graphite powders, conductive compounds, and conductive plastics (col. 2 lines 15-20 :- electrically conducting filled compliant elastomeric layer).
Regarding claim 18, Khandros discloses in figure(s) 1-38 the method of claim 9, wherein the elastic conductive pillars (446; fig. 27) are laterally connected to conductive pads (443,444) supplying the same electrical potential (col. 18 lines 1-5 - “Contact structures 446 are mounted on the pads 443 and are comprised of a skeleton 447 and shell 448 construction” implies same potential).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Khandros in view of Beroz et al. (US 20020031905).
Regarding claim 12, Khandros teaches in figure(s) 1-38 the method of claim 11,
Khandros does not teach explicitly wherein the step of forming the isolation layer on the printed circuit board comprises: forming a sacrificial layer on the printed circuit board; forming a plurality of patterned spaces on the sacrificial layer to expose the conductive pads; filling conductive gel into the patterned spaces and curing the conductive gel.
However, Beroz teaches in figure(s) 1-14 wherein the step of forming the isolation layer on the printed circuit board comprises: forming a sacrificial layer on the printed circuit board; forming a plurality of patterned spaces on the sacrificial layer to expose the conductive pads; filling conductive gel into the patterned spaces and curing the conductive gel (paras. 8-9 - A conductive material, such as metal, may be deposited over the first surface of the removable layer and in each via to form one or more leads … A dielectric layer may then be provided over the conductive material, such as by depositing the dielectric material over the conductive material. The removable layer may then be removed).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khandros by having wherein the step of forming the isolation layer on the printed circuit board comprises: forming a sacrificial layer on the printed circuit board; forming a plurality of patterned spaces on the sacrificial layer to expose the conductive pads; filling conductive gel into the patterned spaces and curing the conductive gel as taught by Beroz in order to provide "a separate bonding step is not required for reliably connecting the leads to the conductive metal sheet. This simplifies the process for making a connection component." (para. 8).
Regarding claim 13, Khandros teaches in figure(s) 1-38 the method of claim 11,
Khandros does not teach explicitly wherein the step of forming the isolation layer on the printed circuit board comprises: forming an isolation layer on a sacrificial layer; forming a plurality of patterned spaces on the isolation layer; filling conductive gel into the patterned spaces and curing the conductive gel to form a plurality of elastic conductive pillars; removing the sacrificial layer; and attaching the elastic conductive pillars together with the isolation layer to the printed circuit board.
However, Beroz teaches in figure(s) 1-14 wherein the step of forming the isolation layer on the printed circuit board comprises: forming an isolation layer (42; figs. 1) on a sacrificial layer (10 ); forming a plurality of patterned spaces on the isolation layer; filling conductive gel into the patterned spaces and curing the conductive gel to form a plurality of elastic conductive pillars (flexible leads 32); removing the sacrificial layer; and attaching the elastic conductive pillars together with the isolation layer to the printed circuit board (16).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khandros by having wherein the step of forming the isolation layer on the printed circuit board comprises: forming an isolation layer on a sacrificial layer; forming a plurality of patterned spaces on the isolation layer; filling conductive gel into the patterned spaces and curing the conductive gel to form a plurality of elastic conductive pillars; removing the sacrificial layer; and attaching the elastic conductive pillars together with the isolation layer to the printed circuit board as taught by Beroz in order to provide "A method of making a connection component includes providing a removable layer having first and second surfaces and forming vias at spaced apart first locations of the removable layer" (abstract).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chiu et al. (US 20190101589) discloses " A testing apparatus for testing an integrated circuit package having a plurality of electrical terminals".
Jardin et al. (US 7126364) discloses "Interface Comprising A Thin PCB With Protrusions For Testing An Integrated Circuit".
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
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