DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5-7, 14-15 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taira et al. U.S. Patent No. 6,014,193 (hereinafter Taira).
Consider claim 1, Taira teaches a display device comprising: a substrate including a display area and a non-display area adjacent to the display area (Figure 18, area corresponding to 60 and area outside of 60); a plurality of data drivers disposed in the display area on the substrate and each including (Figure 18, Data driver 35a-d): a first latch disposed adjacent to one side of the display area facing the non-display area (Figure 15, data latch 52. Figure 18, data driver 35a. Column 24, lines 58-60: the data driver 35 may have the same configuration as the data signal processing circuit 50); a shift register spaced apart from the first latch in a first direction and which sequentially outputs an output signal (Figure 15, shift register 53 and data driver 35b); and a second latch spaced apart from the shift register in the first direction (Figure 15, data latch 52. Figure 18, data driver 35c); wherein the elements include the first latch, the shift register, and the second latch (Figure 15, 52-53. Figure 18, 35a-c); and a plurality of first data lines disposed in the non-display area on the substrate (Figure 18, line from 34 to 35a-d), adjacent to the first latch, connected to the data drivers (Figure 18, adjacent to 35a-c. Figure 15, data latch 52), and to which a data signal in a digital form is applied (column 24, lines 57-60, where a digital data signal is supplied to the data driver 35).
Taira’s figure 18 do not appear to specifically disclose a plurality of pixels disposed in the display area on the substrate and disposed between adjacent elements of each of the plurality of the data drivers, wherein the adjacent elements include the first latch, the shift register, and the second latch, wherein the adjacent elements, in a same data driver and between which the plurality of pixels are disposed, are configured to communicate the data signal in the digital form to each other to generate a data voltage to be provided to the plurality of pixels.
However, Taira teaches in figures 12-13, a plurality of pixels 21a and plurality of data signal processing circuit 50, and further teaches a plurality of pixels disposed in the display area on the substrate and disposed between adjacent elements of each of the plurality of the data drivers (Figures 12-13 and column 21, lines 64-67 and column 22, line 1, plurality of pixels 21a between adjacent elements 50 (e.g. see second row of 21a in figure 13 or second column of 21a in figure 13), wherein the adjacent elements include the first latch, the shift register, and the second latch (Figures 12-13, shift register 53, latch 52), wherein the adjacent elements, in a same data driver and between which the plurality of pixels are disposed, are configured to communicate the data signal in the digital form to each other (Figure 12a, 52-53 communicate to each other (e.g. first row of 50 communicate to second and third row of 50 (see also figure 13)). Figure 12a shows that the D/A located after 52-53. In other words, 52-53 communicate in digital form) to generate a data voltage to be provided to the plurality of pixels (Figure 12a, 50 generates data to be provided to 21a).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide plurality of pixels in between elements as taught by Taira for the purpose of improving the writing time of data signals into the pixel electrodes. A liquid crystal display device having a large capacity such as a large display screen can also drive with an allowance in performance, and the display quality can be improved considerably as suggested in column 25, lines 35-43.
Consider claim 5, Taira teaches all the limitations of claim 1. In addition, Taira wherein the display area includes: first, second, third, and fourth display areas located at outermost edges of the display area, and spaced apart from each other (Figure 18, areas corresponding to the outermost edges); and a fifth display area located between the first, the second, the third, and the fourth display areas (Figure 18, center area of the display).
Consider claim 6, Taira teaches all the limitations of claim 5. In addition, Taira wherein the pixels overlap the first, the second, the third, the fourth, and the fifth display areas (areas in Figure 18), and the first latch, the second latch, and the shift register overlap the first, the second, the third, and the fourth display areas (pixels 63a and 63b located in areas 63a, 63b and 35b (first and second areas); pixels 63c and 63d located in areas 63c, 63d and 35d (third and fourth areas)), not the fifth display area (pixel located in the center area of 63b without overlapping 35b-c).
Consider claim 7, Taira teaches all the limitations of claim 5. In addition, Taira wherein a gap between pixels adjacent in the first direction among the pixels located in the first, the second, the third, and the fourth display areas (Figure 18, gap between pixels 63a and 63b located in areas 63a, 63b and 35b (first and second areas); gap between pixels 63c and 63d located in areas 63c, 63d and 35d (third and fourth areas)) is relatively longer (due to the data driver 35b and 35d separation) than a gap between pixels adjacent in the first direction among the pixels located in the fifth display areas (pixel located in the center area of 63b).
Consider claim 14, Taira teaches all the limitations of claim 1. In addition, Yang teaches a plurality of second data lines electrically connected to the data drivers and the pixels, and to which the data voltage in an analog form is applied (Figure 18, 35a-d and 23; column 24, lines 57-60, DA converter), and wherein the first data lines and the second data lines are spaced apart from each other (Figure 18, lines from 34 to 35a-d; and 23).
Consider claim 15, Taira teaches a display device comprising: a substrate including a display area and a non-display area adjacent to the display aera (Figure 18, area corresponding to 60 and area outside of 60), and including a silicon wafer (Column 14, lines 40-46, silicon); a plurality of data drivers disposed in the display area on the substrate (Figure 18, Data driver) and each including: a first latch disposed adjacent to one side of the display area facing the non-display area (Figure 15, data latch 52. Figure 18, data driver 35a); a shift register spaced apart from the first latch in a first direction and which sequentially outputs an output signal (Figure 15, shift register 53 and data driver 35b); and a second latch spaced apart from the shift register in the first direction (Figure 15, data latch 52. Figure 18, data driver 35c); a plurality of first data lines disposed in the non-display area on the substrate (Figure 18, line from 34 to 35a-d), adjacent to the first latch (Figure 18), and to which a data signal in a digital form is applied (column 24, lines 57-60, where a digital data signal is supplied to the data driver 35); and a plurality of second data lines electrically connected to the data drivers and the pixels (column 24, lines 57-60, DA converter), and to which a data voltage in an analog form is applied (column 24, lines 54-60).
Taira’s figure 18 do not appear to specifically disclose a plurality of pixels disposed in the display area on the substrate and disposed between adjacent elements of each of the plurality of the data drivers, wherein the adjacent elements include the first latch, the shift register, and the second latch, wherein the adjacent elements, in a same data driver and between which the plurality of pixels are disposed, are configured to communicate the data signal in the digital form to each other to generate a data voltage to be provided to the plurality of pixels.
However, Taira teaches in figures 12-13, a plurality of pixels 21a and plurality of data signal processing circuit 50, and further teaches a plurality of pixels disposed in the display area on the substrate and disposed between adjacent elements of each of the plurality of the data drivers (Figures 12-13 and column 21, lines 64-67 and column 22, line 1, plurality of pixels 21a between adjacent elements 50 (e.g. see second row of 21a in figure 13 or second column of 21a in figure 13), wherein the adjacent elements include the first latch, the shift register, and the second latch (Figures 12-13, shift register 53, latch 52), wherein the adjacent elements, in a same data driver and between which the plurality of pixels are disposed, are configured to communicate the data signal in the digital form to each other (Figure 12a, 52-53 communicate to each other (e.g. first row of 50 communicate to second and third row of 50 (see also figure 13)). Figure 12a shows that the D/A located after 52-53. In other words, 52-53 communicate in digital form) to generate a data voltage to be provided to the plurality of pixels (Figure 12a, 50 generates data to be provided to 21a).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide plurality of pixels in between elements as taught by Taira for the purpose of improving the writing time of data signals into the pixel electrodes. A liquid crystal display device having a large capacity such as a large display screen can also drive with an allowance in performance, and the display quality can be improved considerably as suggested in column 25, lines 35-43.
Consider claim 21, Taira teaches an electronic device comprising: a display device (Figure 18); and a power supply configured to provide power to the display device (power in order to turn on the display), wherein the display device comprises: a substrate including a display area and a non-display area adjacent to the display area (Figure 18, area corresponding to 60 and area outside of 60); a plurality of data drivers disposed in the display area on the substrate and each including (Figure 18, Data driver): a first latch disposed adjacent to one side of the display area facing the non-display area (Figure 15, data latch 52. Figure 18, data driver 35a); a shift register spaced apart from the first latch in a first direction and which sequentially outputs an output signal (Figure 15, shift register 53 and data driver 35b); and a second latch spaced apart from the shift register in the first direction (Figure 15, data latch 52. Figure 18, data driver 35c); and a plurality of first data lines disposed in the non-display area on the substrate (Figure 18, line from 34 to 35a-d), adjacent to the first latch, connected to the data drivers (Figure 18), and to which a data signal in a digital form is applied (column 24, lines 57-60, where a digital data signal is supplied to the data driver 35).
Taira’s figure 18 do not appear to specifically disclose a plurality of pixels disposed in the display area on the substrate and disposed between adjacent elements of each of the plurality of the data drivers, wherein the adjacent elements include the first latch, the shift register, and the second latch, wherein the adjacent elements, in a same data driver and between which the plurality of pixels are disposed, are configured to communicate the data signal in the digital form to each other to generate a data voltage to be provided to the plurality of pixels.
However, Taira teaches in figures 12-13, a plurality of pixels 21a and plurality of data signal processing circuit 50, and further teaches a plurality of pixels disposed in the display area on the substrate and disposed between adjacent elements of each of the plurality of the data drivers (Figures 12-13 and column 21, lines 64-67 and column 22, line 1, plurality of pixels 21a between adjacent elements 50 (e.g. see second row of 21a in figure 13 or second column of 21a in figure 13), wherein the adjacent elements include the first latch, the shift register, and the second latch (Figures 12-13, shift register 53, latch 52), wherein the adjacent elements, in a same data driver and between which the plurality of pixels are disposed, are configured to communicate the data signal in the digital form to each other (Figure 12a, 52-53 communicate to each other (e.g. first row of 50 communicate to second and third row of 50 (see also figure 13)). Figure 12a shows that the D/A located after 52-53. In other words, 52-53 communicate in digital form) to generate a data voltage to be provided to the plurality of pixels (Figure 12a, 50 generates data to be provided to 21a).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide plurality of pixels in between elements as taught by Taira for the purpose of improving the writing time of data signals into the pixel electrodes. A liquid crystal display device having a large capacity such as a large display screen can also drive with an allowance in performance, and the display quality can be improved considerably as suggested in column 25, lines 35-43.
Claim(s) 2, 8-10, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taira as applied to claim 1 above, and further in view of Ahn U.S. Patent Publication No. 2003/0090451 (hereinafter Ahn).
Consider claim 2, Taira teaches all the limitations of claim 1. In addition, Taira teaches a driver overlapping at least a portion of the non-display area, and spaced apart from each of the data drivers and pixels in a second direction intersecting with the first direction (Figure 18, 34 and 35a-d).
Taira does not appear to specifically disclose a gamma driver.
However, in a related field of endeavor, Ahn teaches a data-driving IC in figure 4 and further teaches a gamma driver (figure 4, 90).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a gamma driver or voltage part as taught by Ahn in order to divide a plurality of gamma reference voltages from a gamma reference voltage generator for each gray level to output the divided gamma reference voltages as suggested in [0099].
Consider claim 8, Taira teaches all the limitations of claim 5. In addition, Taira teaches wherein the elements of the data drivers are disposed between the pixels (Figure 18, Data driver 35a-d), and further include a plurality of digital-analog converters overlapping the first, second, third, and fourth display areas (column 24, lines 57-60, D/A and areas comprising 35a-d).
Taira does not appear to specifically disclose a demux circuit.
However, in a related field of endeavor, Ahn teaches a demux circuit 84 in figure 4.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a demux circuit as taught by Ahn with the benefit that the demultiplexor array 84 selectively applies the pixel voltage signals from the third multiplexor array 80 to 2n data lines in response to the first and second selection control signals as suggested in [0111].
Consider claim 9, Taira and Ahn teach all the limitations of claim 8. In addition, Taira teaches wherein the circuit is disposed adjacent to the fifth display area (Figure 18, 35b/c are adjacent to center region of 63b). Furthermore, Ahn teaches demux circuit 84 in figure 4, see motivation to combine in claim 8.
Consider claim 10, Taira and Ahn teach all the limitations of claim 8. In addition, Taira teaches wherein the pixels are arranged in a second direction intersecting with the first direction (Figure 18, pixels in 63a-d), and the digital-analog converters are arranged alternately with the pixels in the first direction (Figure 18, data driver 35a-d; column 24, lines 57-60, D/A).
Consider claim 16, it includes the limitations of claim 2 and thus rejected by the same reasoning.
Consider claim 18, it includes the limitations of claim 8 and thus rejected by the same reasoning.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taira and Ahn as applied to claim 8 above, and further in view of Gondo U.S. Patent Publication No. 2012/0127143 (hereinafter Gondo).
Consider claim 11, Taira and Ahn teach all the limitations of claim 8.
Taira does not appear to specifically disclose wherein the data drivers further include a level shifter, and the level shifter is disposed between the second latch and a digital-analog converter adjacent to the second latch among the plurality of digital-analog converters.
However, in a related field of endeavor, Gondo teaches a display driving device in figure 7, and further teaches wherein the data drivers further include a level shifter, and the level shifter is disposed between the second latch and a digital-analog converter adjacent to the second latch among the plurality of digital-analog converters (Figure 7, 63, 64 and D-A).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a level shifter as taught by Gondo with the benefit that when the output data from the second latch section 63 are of a low voltage type (e.g., 3V type), the level shifter 64 level-shifts those data to a high voltage type (for example, 15V type) and then outputs the data after the level shift through the data output terminals as suggested in [0107].
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taira as applied to claim 1 above, and further in view of Yang et al. U.S. Patent Publication No. 2022/0223573 (hereinafter Yang).
Consider claim 12, Taira teaches all the limitations of claim 1. In addition, Taira teaches pixels and the data drivers and overlapping the display area (Figure 18, 35a-d and 63a-d).
Taira does not appear to specifically disclose an encapsulation layer disposed on the display area and the non-display area, and wherein the non-display area includes: a first non-display area overlapping the encapsulation layer; and a second non-display area not overlapping the encapsulation layer.
However, in a related field of endeavor, Yang teaches a display device in figure 3 and further teaches an encapsulation layer disposed on the display area and the non-display area (Figure 3, ENC, DA and NDA), and wherein the non-display area includes: a first non-display area overlapping the encapsulation layer (Figure 3, NDA, ENC); and a second non-display area not overlapping the encapsulation layer (Figure 3, NDA and ENC).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide encapsulation as taught by Yang’s figure 3 with the benefit that an encapsulation member ENC disposed across the display area DA and the non-display area NDA to encapsulate the display element layer DEP as suggested in [0061].
Consider claim 13, Taira and Yang teach all the limitations of claim 12. In addition, Yang teaches wherein the first data lines overlap the first non-display area (Figure 3, SGL, see motivation to combine in claim 12).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taira and Ahn as applied to claim 18 above, and further in view of Yang.
Consider claim 19, it includes the limitations of claim 12 and thus rejected by the same reasoning.
Consider claim 20, it includes the limitations of claim 13 and thus rejected by the same reasoning.
Allowable Subject Matter
Claims 3-4, 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior arts do not appear to disclose the limitations of claim 3 (or claim 17) in combination to the limitation of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 02/16/2026 have been fully considered but they are not persuasive.
On pages 11-12, Applicant argues that “FIG. 18 of Taira the Examiner relies on merely discloses that the data driver 35a provides the data voltage to pixels in the block 63a, and the data driver 35b provides the data signal to pixels in the block 63b. FIG. 18 of Taira does not disclose that the data driver 35a and the data driver 35b communicate data signals to generate the data voltage to be provided to the pixels in the block 63a, different from the claimed invention.” The Office respectfully disagrees for the following reasons.
Taira teaches in figures 13 and 15, data signal processing circuits 50 communicate to generate data voltage to the pixels 21a.
On pages 11-12, Applicant argues that “while FIG. 15 of Taira the Examiner does not disclose that the picture element 21a (allegedly corresponding to the recited "pixel") is located between the data latch 52 and the shift register 53 in the same data driver 35a, different from the claimed invention.” The Office respectfully disagrees for the following reasons.
Taira teaches in figures 12-13, column 21, lines 64-67 and column 22, line 1, plurality of pixels 21a between adjacent elements 50 (e.g. see second row of 21a in figure 13 or second column of 21a in figure 13), where elements 50 comprises latch 52 and shift register 53. Consequently, these arguments have been considered but they are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621