DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 11/25/2025. These drawings are acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4-6, and 8-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a first scan line" in both lines 7 and 16, followed by “the first scan line” in line 17, which poses an indefinite antecedent basis in the claim. It is unclear if these all refer to the same first scan line or a different scan line. For the purpose of art rejection below examiner interprets the first scan line to be one scan line. Claims 14 and 16 recite similar limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 8, and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US PGPub 2024/0078976) in view of Guo et al. (US PGPub 2023/0410744).
Regarding claim 1, Cheng discloses a display panel ([0139], “An exemplary embodiment also provides a display panel which may include the above pixel drive circuit. The display panel may be applied to a display apparatus such as a mobile phone, a tablet computer, and a television”), comprising a pixel circuit (figs. 49-51), wherein the pixel circuit comprises:
a driving module (figs. 49 and 50, drive circuit 11);
a gate reset module (figs. 49 and 50, first initialization circuit 14) electrically connected between a first signal line and a control node (figs. 49 and 50, element 14 connected between Vi1 and N0);
a threshold compensation module (figs. 49 and 50, compensation control circuit 13) electrically connected between an output terminal of the driving module and the control node (figs. 49 and 50, element 13 connected between N3, output of the drive circuit 11, and N0);
a first scan line (fig. 50, signal S1);
a data writing module (figs. 49 and 50, data writing circuit 41); and
a control module (figs. 49 and 50, first control circuit 12) electrically connected between the control node and a control terminal of the driving module (figs. 49 and 50, element 12 electrically connected between N0 and N1, the control node of element 11);
wherein a driving cycle of the pixel circuit comprises an initialization period, a charging period, and a light-emitting control period ([0375], “As shown in FIG. 51, when the pixel circuit according to at least one embodiment of the present disclosure shown in FIG. 50 is working, a display cycle includes an initialization phase t1, a data writing phase t2, and a light emitting phase t3 which are set sequentially), the gate reset module is turned on during the initialization period (fig. 51, R1 turned on during t1), the threshold compensation module is turned on at least during the charging period (fig. 51, S2 turned on during t2), and the control module is turned on during the initialization period and the charging period and is turned off during the light-emitting control period (fig. 51, S1 turned on during t1 and t2, where as shown in fig. 50 element 12 is an n-type transistor and thus a high signal at the control node is turning on),
,
wherein the first scan line provides a first enable level during the initialization period and a second enable level during the charging period (fig. 51, where signal S1 is high during time t1 and t2),
wherein a control terminal of the control module (fig. 50, signal line S1), and during the initialization period and the charging period, the control module (fig. 51, signal S1 is high during t1 and t2 which turns on transistor T1); and
the data writing module is electrically connected between a data line and an input terminal of the driving module (fig. 50, transistor T8 connected between D1 and N2), a control electrode of the data writing module is electrically connected to a second scan line (fig. 50, signal S2), and during the charging period, the data writing module is turned on in response to an enable level provided by the second scan line (fig. 51, signal S2 is low during period t2 which turns on transistor T8).
While Cheng teaches a scan signal connected to the control module set to enable a transistor during the initialization period and during the charging period, it has been known to have a space between the initialization period and the charging period. Additionally, while Cheng teaches a control module and a threshold compensation module connected to scan signals, it has been known to have the control module and threshold compensation module connected to the same scan signal. In a similar field of endeavor of pixel circuitry of a display panel, Guo discloses wherein a control terminal of the control module is electrically connected to a first scan line ([0038], “The control terminal of the compensation module 300 accesses a first light emission control signal EMB” and fig. 7, control of transistor M4); and
wherein the first scan line provides a first enable level during the initialization period and a second enable level during the charging period (fig. 10, signal EMB low during t11 and t12, and t2 period), and there is an interval between the first enable level and the second enable level (fig. 10, time between t12 and t2);
a control terminal of the control module and a control terminal of the threshold compensation module are both electrically connected to a first scan line (fig. 7, control of transistor M4 and module 300 connected to EMB signal), and during the initialization period and the charging period, the control module and the threshold compensation module are turned on in response to an enable level provided by the first scan line (fig. 10, EMB low during t11, t12 and period t2 which turns on p-type transistors).
In view of the teachings of Cheng and Guo, it would have been obvious to one of ordinary skill in the art to include the interval between the first enable level and the second enable level, as taught by Guo, in the system of Cheng, for the purpose of improving a flicker problem by having a leakage current of a current leakage suppression module transistor be small and the potential of the gate more stable (Guo: [0093]).
Regarding claim 2, Cheng further discloses wherein a control terminal of the control module is electrically connected to a first scan line (fig. 50, line S1); and
wherein a period during which an enable level is provided by the first scan line covers the initialization period and the charging period (fig. 51, signal S1 high during t1 and t2).
Regarding claim 4, Cheng further discloses further comprising a first light-emitting control module and a second light-emitting control module (figs. 49 and 50, light emitting control circuit 31 with includes transistors T5 and T6),
wherein a control terminal of the control module is electrically connected to a first scan line (fig. 50, line S1); and
a control terminal of the first light-emitting control module and a control terminal of the second light-emitting control module are both electrically connected to a light-emitting control signal line (fig. 50, signal line E1), the first light-emitting control module is electrically connected between a first power line and an input terminal of the driving module (fig. 50, transistor T5), and the second light-emitting control module is electrically connected between the output terminal of the driving module and a light-emitting element (fig. 50, transistor T6);
wherein a non-enable level provided by the light-emitting control signal line covers an enable level provided by the first scan line (fig. 51, where E1 high is non-enable for the p-type transistors T5 and T6 and S1 high is enable for the n-type transistor T1), and a width of the non-enable level provided by the light-emitting control signal line is greater than a width of the enable level provided by the first scan line (fig. 51, where E1 is high before t1 and remains high between t2 and t3).
Regarding claim 8, Cheng further discloses wherein a control terminal of the control module is electrically connected to a first scan line (fig. 50, signal S1), and during the initialization period and the charging period, the control module is turned on in response to an enable level provided by the first scan line (fig. 51, signal S1 is high during t1 and t2 which turns on an n-type transistor); and
a control terminal of the threshold compensation module is electrically connected to a second scan line (fig. 50, signal S2), and during the charging period, the threshold compensation module is turned on in response to an enable level provided by the second scan line (fig. 51, signal S2 is low during t2 period which tuns on a p-type transistor).
Regarding claim 11, Cheng further discloses wherein a control terminal of the gate reset module is electrically connected to the first signal line (fig. 50, R1 line);
during the initialization period, the gate reset module is turned on in response to an enable level provided by the first signal line, and a voltage of the enable level provided by the first signal line is written into the control node (figs. 50 and 51, R1 signal turns on transistor T3 in t1 period); and
during the charging period and the light-emitting control period, the gate reset module is turned off in response to a non-enable level provided by the first signal line (fig. 51, R1 signal in the t2 period).
Regarding claim 12, Cheng further discloses further comprising an anode reset module (figs. 49 and 50, second initialization circuit 32), wherein the anode reset module is electrically connected between an anode reset line and a light-emitting element (fig. 50, transistor T7 connected between Vi2 and light emitting diode O1), and the anode reset module is turned on during the initialization period or the charging period (fig. 51, S4 signal turns on the transistor during t1);
wherein the gate reset module comprises a gate reset transistor, a voltage of the enable level provided by the first signal line is V1, a voltage provided by the anode reset line is V2, V1+|Vth|<V2, and Vth is a threshold voltage of the gate reset transistor ([0360], “A gate of the seventh transistor T7 is electrically connected with the fourth scan line S4, a drain of the seventh transistor T7 is electrically connected with the second initialization voltage line, and a source of the seventh transistor T7 is electrically connected with the anode of the organic light emitting diode O1. The second initialization voltage line is used for providing a second initialization voltage Vi2”).
Regarding claim 13, Cheng further discloses wherein the gate reset module comprises a gate reset transistor (fig. 50, transistor T3), a first electrode of the gate reset transistor is electrically connected to the first signal line (fig. 50, signal line Vi1), a second electrode of the gate reset transistor is electrically connected to the control node (fig. 50, node N0), and the gate reset transistor comprises a channel ([0176], “The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. It is to be noted that, in the specification, the channel region refers to a region through which the current mainly flows” where a channel is a known part of a transistor); and
the threshold compensation module comprises a threshold compensation transistor (fig. 50, transistor T2), a first electrode of the threshold compensation transistor is electrically connected to the output terminal of the driving module (fig. 50, node N3), a second electrode of the threshold compensation transistor is electrically connected to the control node (fig. 50, node N0), and the threshold compensation transistor comprises a channel ([0176], “The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. It is to be noted that, in the specification, the channel region refers to a region through which the current mainly flows” where a channel is a known part of a transistor).
Claim 14 is a method for driving a display panel drawn to the display panel of claim 1 and is therefore interpreted and rejected based on similar reasoning.
Regarding claim 15, Cheng further discloses wherein a control terminal of the gate reset module is electrically connected to the first signal line (fig. 50, signal line R1);
wherein the method further comprises:
controlling the first signal line to provide an enable level during the initialization period, so that the gate reset module is turned on in response to the enable level provided by the first signal line to transmit a voltage of the enable level provided by the first signal line to the control node (fig. 51, signal R1 set to low during t1 period which turns on a p-type transistor); and
controlling the first signal line to provide a non-enable level during the charging period and the light-emitting control period, so that the gate reset module is turned off in response to the non-enable level provided by the first signal line (fig. 51, signal R1 set to high during t2 and t3 which turns off a p-type transistor).
Regarding claim 16, the combination of Cheng and Guo further discloses a display apparatus (Cheng: [0139], “An exemplary embodiment also provides a display panel which may include the above pixel drive circuit. The display panel may be applied to a display apparatus such as a mobile phone, a tablet computer, and a television”), comprising a display panel, wherein the display panel is within the scope of claim 1 and is therefore interpreted and rejected based on similar reasoning.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng and Guo in view of Guo et al (US PGPub 2023/0343294) hereinafter referred to as Guo ‘294.
Regarding claim 5, the combination of Cheng and Guo further discloses further comprising a first light-emitting control module and a second light-emitting control module (Cheng: fig. 50, transistor T5 and transistor T6), wherein a control terminal of the first light-emitting control module and a control terminal of the second light-emitting control module are both electrically connected to a light-emitting control signal line (Cheng: fig 50; signal E1), the first light-emitting control module is electrically connected between a first power line and an input terminal of the driving module (Cheng: fig. 50, transistor T5), and the second light-emitting control module is electrically connected between the output terminal of the driving module and a light-emitting element (Cheng: fig. 50, transistor T6).
While Cheng and Guo teaches control signals for the control module and for the light-emitting control modules, it has been known to use one signal which is inverted to control both groups of modules. In a similar field of endeavor of pixel circuitry within a display device, Guo ‘294 discloses wherein a control terminal of the control module is electrically connected to the light-emitting control signal line through an inverter, the control module is turned on in response to a first enable level, and the first enable level is opposite to a non-enable level provided by the light-emitting control signal line ([0128], “The signal on the electric leakage control signal line EMB and the signal on the light-emitting control signal line EM are inverted signals. Only an inverter is arranged at an output terminal of the light-emitting control driver circuit, and the signal output by the light-emitting control driver circuit is output to the electric leakage control signal line EMB through the inverted signal of the inverter. Therefore, a scan circuit composed of a complex shift register for the electric leakage control signal line EMB does not need to be designed, so that the circuit device in the frame region of the display panel can be reduced, and the design of the narrow frame of the display panel can be easily achieved”).
In view of the teachings of Cheng, Guo and Guo ‘294, it would have been obvious to one of ordinary skill in the art to include the inverter of Guo ‘294, in the system of Cheng and Guo, so that the circuit device in the frame region of the display panel can be reduced, and the design of the narrow frame of the display panel can be easily achieved (Guo ‘294: [0128]).
Regarding claim 6, the combination of Cheng and Guo further discloses further comprising a first light-emitting control module and a second light-emitting control module (Cheng: fig. 50, transistor T5 and T6), wherein a control terminal of the first light-emitting control module and a control terminal of the second light-emitting control module are both electrically connected to a light-emitting control signal line (Cheng: fig. 50, signal E1), the first light-emitting control module is electrically connected between a first power line and an input terminal of the driving module (Cheng: fig. 50, transistor T5), and the second light-emitting control module is electrically connected between the output terminal of the driving module and a light-emitting element (Cheng: fig. 50, transistor T6);
wherein a control terminal of the control module is electrically connected to a (Cheng: fig. 50, signal S1), and the control module is turned on in response to a non-enable level provided by the (Cheng: figs. 50 and 51, where transistor T1 is a n-type transistor and is turned on when S1 is high).
While Cheng and Guo teaches turning on a control module in response to a non-enable level, it has been known to have one control signal line controlling multiple transistor modules. In a similar field of endeavor of pixel circuitry within a display device, Guo ‘294 discloses wherein a control terminal of the control module is electrically connected to the light-emitting control signal line ([0128], “Only an inverter is arranged at an output terminal of the light-emitting control driver circuit, and the signal output by the light-emitting control driver circuit is output to the electric leakage control signal line EMB through the inverted signal of the inverter” where the EM and EMB are the same signal at the input of the inverter).
In view of the teachings of Cheng, Guo and Guo ‘294, it would have been obvious to one of ordinary skill in the art to have a control terminal of the control module electrically connected to the light-emitting control signal line, as taught by Guo ‘294, within the system of Cheng and Guo so that the circuit device in the frame region of the display panel can be reduced, and the design of the narrow frame of the display panel can be easily achieved (Guo ‘294: [0128]).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng and Guo in view of Kim (US PGPub 2023/0245616).
Regarding claim 9, the combination of Cheng and Guo further discloses further comprising a capacitor module (Cheng: fig. 50, capacitor 42), wherein the capacitor module is electrically connected between a first power line and a (Cheng: fig. 50, capacitor 42 connected to VDD and node N1 which is connected to node N0 through transistor T1).
While Cheng and Guo discloses a capacitor indirectly connected to the control node, it has been known to connect the capacitor between the power line and a control node. In a similar field of endeavor of pixel circuitry, Kim discloses the capacitor module is electrically connected between a first power line and the control node (fig. 8, capacitor CN3 connected between ELVDD and node N3).
In view of the teachings of Cheng, Guo and Kim, it would have been obvious to one of ordinary skill in the art to include the capacitor of Kim in the system of Cheng and Guo, for the purpose of providing a known structure where a voltage difference between the third node N3 and the fourth node N4 may be reduced, and the leakage current flowing through the compensation transistors T3_2 and T3_3 may be reduced which improves the display device (Kim: [0099]).
Regarding claim 10, the combination of Cheng and Guo further discloses further comprising a capacitor module (Cheng: fig. 50, capacitor 42), (Cheng: fig. 50, capacitor 42 connected between VDD and node N1).
While Cheng and Guo teaches a capacitor module, it has been known to have two capacitors in parallel acting as the capacitor module. In a similar field of endeavor of pixel circuitry, Kim discloses wherein the capacitor module comprises a first capacitor sub-module and a second capacitor sub-module (fig. 8, capacitors CST and CN3), the first capacitor sub-module is electrically connected between a first power line and the control node (fig. 8, capacitor CN3 connected between ELVDD and N3), and the second capacitor sub-module is electrically connected between the first power line and the control terminal of the driving module (fig. 8, capacitor CST connected between ELVDD and N4).
In view of the teachings of Cheng, Guo and Kim, it would have been obvious to one of ordinary skill in the art to include the capacitors of Kim in the system of Cheng and Guo, for the purpose of providing a known structure where a voltage difference between the third node N3 and the fourth node N4 may be reduced, and the leakage current flowing through the compensation transistors T3_2 and T3_3 may be reduced which improves the display device (Kim: [0099]).
Response to Arguments
Applicant's arguments filed 11/25/2025 have been fully considered but they are not persuasive. Regarding claims 1, 14 and 16, Applicants argue, the combination of Cheng and Guo does not disclose “a control terminal of the control module is electrically connected to a first scan line, wherein the first scan line provides a first enable level during the initialization period and a second enable level during the charging period and there is an interval between the first enable level and the second enable level” (pages 12-14), however Examiner respectfully disagrees. Examiner maintains that as claimed the first enable level and the second enable level may be the same level, but requires including an interval in between”. Guo teaches at [0038], “the control terminal of the compensation module 300 accesses a first light emission control signal EMB”. It is known that a gate circuit can emit both an emission control signal and a scan signal which are driving signals used to control pixels. Fig. 10 of Guo and Applicants Fig. 4 both show three signals where the timing of Guo’s S2 and S1 aligns with the timing of Applicants’ S2 and S3 and the timing of Guo’s EMB lines up with the timing of Applicants’ S1. The connection of Guo’s transistor M4 where EMB controls the gate of M4 in fig. 7 lines up with the connection of Applicant’s transistor M0 in fig. 2 where S1 controls the gate of M0. Guo teaches at fig. 10 the EMB signal which goes to an enable level at t11/t12 (as a combined first interval) and t2 with an interval that is not labeled in between t12 and t2. Further, Guo teaches in fig. 7 the EMB signal is connected to the control of transistor M4 and transistor M1 (the compensation module 300). Therefore, the combination of Cheng and Guo teaches the limitations of claims 1, 14 and 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
He et al. (US PGPub 2024/0087518) discloses a structural diagram of a pixel (fig. 3).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629