DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 21 – 37 in the reply filed on 06/25/2026 is acknowledged.
Claims 38 – 40 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/25/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the “cell-select transistor pairs” (claimed 5 times in claim 21; claimed 2 times in claim 24, claimed 4 times in claim 25; claimed 6 times in claim 26; claimed 5 times in claim 27, claimed 4 times in claim 28; and claimed 5 times in claim 30; claimed 1 time in claim 32, claimed 1 time in claim 33, claimed 1 time in claim 34; claimed 5 times in claim 38; claimed 2 times in claim 39) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21 – 37 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In the claims, the limitation “cell-select transistor pairs” is not found in the original specification.
Further in claim 38, the “unique magneto resistive memory cell-select transistor pair” is not found in the original specification.
These are considered as new matters as claims 21 – 37 are not originally filed claims.
Claims 22 – 29 and 31 – 37 are rejected for either including new-mattered limitation shown above, or for being dependent from rejected independent claim.
Appropriate clarification is required in order to overcome this type of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21 – 23 and 29 – 36 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Braun et al. (US Pat Pub 2006/0092689).
Regarding claims 21 and 30, Braun et al. disclose a magnetoresistive memory (figs. 1 – 10 and all related texts), comprising:
a magnetoresistive memory array (for example the memory array of fig. 8) including
a plurality of bit lines (BL1 – BL8, fig. 8) arranged in a plurality of columns (as shown),
(ii) a plurality of source lines arranged in a plurality of rows (referred to as the lines connecting the ground potential to the sources of the X1## transistors whose gates are controlled by word lines RWL1 – WL4, fig. 4b or 9a, for example), and
(iii) a plurality of magnetoresistive memory cell-select transistor pairs (referred to as the column select transistors CS1, CS2…, CSn, etc… and RWL select transistors X111 – X1n1, etc…, as shown in fig. 4b), wherein:
the plurality of bit lines includes a plurality of regular bit lines (BL1 – BLn, fig. 4b or 9a) and a plurality of reference bit lines (referred to as bit lines connecting reference cells RC1, Rc2 to reference column select switches CSref, fig. 4b or 9a), and
each reference bit line is associated with a group of a predetermined number of the regular bit lines of the plurality of bit lines, wherein each reference bit line is associated with a different group of the predetermined number of the regular bit lines of the magnetoresistive memory array (for example in fig. 4b, two reference bit lines connected to X3R1 and X3R2 on the right side of fig. 4b provide reference voltage point for the corresponding group of regular bit lines BL1-BLn of the group of regular bit lines connected to the transistor switch X3. Fig. 9a also illustrates the same);
a sense amplifier (18 of fig. 4b or fig. 9a), coupled to the magnetoresistive memory array (as shown), to determine a data state of a selected magnetoresistive memory cell of a selected one of the magnetoresistive memory cell-select transistor pairs using a sense reference (provided to the inverted (-) input of the sense amplifier 18, fig. 4b or 9a), wherein the sense amplifier includes a first input and a second input (the + non-inverting input connected to switch X3 and the -negative inverting input connects to drains of the reference transistors X3R1/X3R2, fig. 4b/9a);
a reference generator circuit (see abstract, reference current source), coupled to the first input of the sense amplifier (to the inverting input terminal of the sense amplifier 18), to generate the sense reference to apply the sense reference to the first input of the sense amplifier, the reference generator circuit (abstract: more than four reference magnetic memory cells…) including:
a resistor circuit having at least one trimmable resistor and at least one non-trimmable resistor connected in series, wherein the resistor circuit includes first and second terminals and a programmable resistance, and wherein the first terminal is coupled, in operation, to the reference bit line which is associated with a selected regular bit line of the selected one of the magnetoresistive memory cell-select transistor pair(referred to in para 0019, 0020, 0023, etc…, referred to as trimmed resistors to desired resistance value for the reference voltage generator. See figs. 6 and 7), and
a tracking circuit, coupled to the resistor circuit and the first input of the sense amplifier, to adjust the sense reference which is applied to the first input of the sense amplifier in accordance with a temperature coefficient that matches a change in resistance, over temperature, of the magnetoresistive memory cell of the magnetoresistive memory cell-select transistor pair, wherein the tracking circuit is connected to the second terminal of the resistor circuit and the first input of the sense amplifier (see para 0079, 0086, etc…, for tracking temperature change for the reference current source); and
a column selection circuit (including transistors X21 – X2n for the regular bit lines and the transistors over the reference side whose gates connect to signal CSref, fig. 4b or 9a), coupled to each of the plurality of bit lines (BL1-BLn) and the reference generator circuit (on the right portion of fig. 4b or 9a), to responsively couple:
the reference bit line (bit lines connecting reference resistors network RC1/RC2 to the reference column select transistor whose gates connect to signal CSref), which is associated with the selected regular bit line, to the first input of the sense amplifier via the resistor circuit (negative inverting input of sense amplifier 18), and
the selected regular bit line to the second input of the sense amplifier (one of bit lines BL1 – BLn selected and coupled to the positive non-inverting input of amplifier 18), wherein the selected regular bit line is associated with the selected magnetoresistive memory cell of the selected one of the magnetoresistive memory cell-select transistor pairs (as shown in fig. 4b or 9a).
Regarding claims 22, 23, 31 and 35, Braun et al. also disclose the magnetoresistive memory of claim 21,
wherein the tracking circuit is configured to adjust the temperature coefficient based on a reference current associated with the resistor circuit,
wherein the tracing circuit is configured to adjust a reference current associated with the resistor circuit and the reference bit line based on a temperature of the magnetoresistive memory array (see para 0086).
Regarding claims 29 and 36, Braun et al. also disclose the magnetoresistive memory of claim 21, wherein the tracing circuit is a current mirror having a current trim circuit configurable to adjust a temperature dependent magnitude thereof (current mirror taught in para 0025 – 0028. See also para 0062, 0066, 0068, 0069, 0082, 0083, etc…).
Regarding claim 32, Braun et al. also disclose the magneto resistive memory of claim 30, wherein each magnetoresistive memory cell of the reference magnetoresistive memory cell-select transistor pair (each of for example, RC1 or RC2, fig. 4b or 9a, which is one of fig. 6a, 6b, or 7) which is associated with the reference bit line includes first and second electrode (referred to, for example in fig. 6a, electrode N1 and N2), wherein the first electrode is connected to the reference bit line (N1 is connected to the reference bit line, according to fig. 4b, N2 is connected to the Sources of the reference word lines RWLref, fig. 4b or 9a).
Regarding claim 33, Braun et al. also disclose the magnetoresistive memory of claim 32, further including: a bridge element which is connected to the second electrode of each magnetoresistive memory cell of the reference magnetoresistive memory cell-select transistor pair which is associated with the reference bit line (see para 0013 for disclosure of “MTJs can be arranged in circuit configurations such as BRIDGES wherein…”).
Regarding claim 34, Braun et al. also disclose the magnetoresistive memory of claim 30, further including a plurality of source lines, wherein each row of the magnetoresistive memory array includes a common source line connected to each magnetoresistive memory cell-select transistor pair of the common row (source lines are referred to, in fig. 4b or 9a, as lines connecting ground potential to the sources of the word lines RWL# and RWLref, fig. 4b and 9a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Braun et al. (US Pat Pub 2006/0092689) in view of Sandhu et al. (US Pat Pub 2017/0045905).
Regarding claim 37, Braun et al. disclose the magnetoresistive memory of claim 30, except wherein: the tracking circuit includes n-well resistors.
This feature is taught by Sandhu et al. (see para 0060, “n-well resistor… may have a characteristic of a positive temperature coefficient…”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the filing date of the present application, to combine the references as cited, so that positive temperature coefficient may be provided for tracking purposes.
Allowable Subject Matter
Claims 24 – 28 and 37 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (provided the 112a rejection in paragraph 7 above overcome).
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the magnetoresistive memory as set forth above, further comprising, in combination, the features and limitations additionally claimed in claims 24 – 28 and 37.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 July 15, 2026
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