Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1
b. Pending: 1-7
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 11/1/2024 and 7/3/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor memory device and method with memory type that depends on proximity to contact region.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Narku et al. (US 20220270680) in view of Nojima et al. (US 20220020681).
Regarding independent claim 1, Narku discloses a method of operating a semiconductor memory device (Figs. 1-11), the method comprising:
receiving a command for a target memory block ([0045] describes storage device controller 118 may receive a command from a host device (e.g., CPU 102) for a target memory chip. Here examiner equates memory chip with memory block) among a plurality of memory blocks (Fig. 1 shows multiple memory chips 116) from a memory controller (Fig. 1 shows chip controller 126 and memory controller 112);
determining an operation parameter for performing an operation corresponding to the command ([0115] describes control circuitry determines one or more parameters indicative of one or more properties of the electrical path through the memory cell), based on a type of the target memory block ([0040] describes that computer system 100 may include multiple different types of storage devices, as for example based on speed, technology, or form factor of memory in various embodiments. [0101], [0103] describes that control circuitry determines a voltage or other control signal (these are parameters) depending on the type of current source); and
performing the operation on the target memory block, based on the determined operation parameter (Fig. 8 at step 802 describes receiving instructions to perform an operation on memory cell and Fig. 9 at step 830 and [0105] describes that control circuit 312 performs the operation on the memory cell).
Nojima explicitly teaches first and second memory blocks and contact regions (claim 2).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Nojima to Narku in order to provide with semiconductor memory device with specific arrangements of blocks and contact areas as taught by Nojima (Abstract).
Regarding claim 5, Narku and Nojima together disclose all the elements of claim 1 as above and through Narku further
the command is a program command, and the operation parameter is a parameter included in a program operation for the target memory block (Fig. 1 and [0043] describes that program control logic 124 which is operable to control the programming sequence performed when data is written to or read from a memory chip 116. In various embodiments, program control logic 124 may provide the various voltages (or information indicating which voltages should be provided) that are applied to memory cells during the programming and/or reading of data (or perform other operations associated with read or program operations)).
Regarding claim 6, Narku and Nojima together disclose all the elements of claim 1 as above and through Narku further
the command is a read command, and the operation parameter is a parameter included in a read operation for the target memory block (Fig. 1 and [0043] describes that program control logic 124 which is operable to control the programming sequence performed when data is written to or read from a memory chip 116. In various embodiments, program control logic 124 may provide the various voltages (or information indicating which voltages should be provided) that are applied to memory cells during the programming and/or reading of data (or perform other operations associated with read or program operations)).
Regarding claim 7, Narku and Nojima together disclose all the elements of claim 1 as above and through Narku further
the command is an erase command, and the operation parameter is a parameter included in an erase operation for the target memory block (Figs. 1-2, [0043] and [0051] describes that program control logic 124 may provide the various voltages (or information indicating which voltages should be provided) that are applied to memory cells during the programming and/or reading of data (or perform other operations associated with read or program operations), perform error correction, and perform other suitable functions. Here examiner asserts that erase is form of program/write operation).
Also, Nojima explicitly teaches erase operation ([0049]-[0050] describes command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Narku et al. (US 20220270680) in view of Nojima et al. (US 20220020681) and further in view of Yip et al. (US 20150001613).
Regarding claim 2, Narku and Nojima together disclose all the elements of claim 1 as above and through Yip further
a contact region is formed between the plurality of memory blocks, and among the plurality of memory blocks, a type of a memory block that is not adjacent to the contact region is a first memory block, and a memory block adjacent to the contact region is a second memory block (Claim 24 recites a memory array, the memory array comprising a stack of conductive tiers and a stair step structure between first and second portions of the memory array, wherein the stair step structure comprises contact regions for respective conductive tiers of the stack of conductive tiers).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Yip to modified Narku in order to provide with three-dimensional semiconductor devices that include stair step structures defining contact regions, and related methods of forming and of operating such semiconductor devices as taught by Yip ([0001]).
Regarding claim 3, Narku, Nojima and Yip together disclose all the elements of claim 2 as above and through Narku further
determining the operation parameter comprises: checking the type of the target memory block ([0045] describes determine a target memory chip for the command); and
selecting a first parameter when the target memory block is the first memory block ([0076] describes the control circuitry 312 may apply a formula, check a database, etc., based on the selected memory cell 300 and the corresponding bitline and wordline to determine one or more parameters for controlling the current sources 314, 316. In one embodiment, the control circuitry 312 may determine an amplitude and/or duration of current to be supplied by the coarse-grained current source 316 by multiplying a length of the electrical path of the bitline by a first pre-determined constant then adding a length of the electrical path of the wordline multiplied by a second pre-determined constant).
Regarding claim 4, Narku, Nojima and Yip together disclose all the elements of claim 3 as above and through Narku further
determining the operation parameter further comprises: selecting a second parameter different from the first parameter when the target memory block is the second memory block ([0094] describes control circuitry 312 may apply a formula, check a database, etc., based on the selected memory cell 714 and the corresponding bitline 740 and wordline 750 to determine one or more parameters for controlling the current sources 724, 728. In one embodiment, the control circuitry 312 may determine an amount of charge to supply by the coarse-grained current source 728 by multiplying a length of the electrical path of the bitline 740 by a first pre-determined constant then adding a length of the electrical path of the wordline 750 multiplied by a second pre-determined constant) .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 5/30/2026
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