Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hrinya et al. (US Pub # 2021/0099073) in view of Yoon et al. (US Pub # 2015/0214827).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Hrinya et al. teach a switching converter (see Fig.1 and paragraph 0014-0021, unit 100 is converter), comprising: a first switch connected to an input voltage source and an inductor; a second switch connected to a ground terminal (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, first switch Q1 connected to input voltage Vin, second switch Q2 connected to ground, L1 is inductor) and the inductor; and a control circuit connected to the first switch and the second switch, the control circuit configured to control the first switch and the second switch, wherein the first switch and the second switch are configured to regulate charging and discharging of the inductor (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, (104+120+108+110) is controller, controlling Q1 and Q2 switch), and wherein the control circuit is configured to compare an output voltage of the switching converter with a threshold voltage using at least one comparator; detect an overshoot in the output voltage based on the comparison (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, comparator 104 compare output voltage Vout with threshold voltage Vset); and perform at least one of disable, based on the detection of the overshoot in the output voltage, each of the first switch and the second switch to increase a slope of an inductor discharge current flowing across the inductor such that the overshoot in the output voltage is reduced; or activate a dummy load circuit connected at an output of the switching converter to reduce an overshoot in the output voltage (see Fig.1-8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, dummy load cancels output voltage overshoot, see specially paragraph 0035).
Even though Hrinya et al. teach wherein the first switch and the second switch are configured to regulate storing energy / dissipating energy of the inductor but silent exclusively charging and discharging of the inductor.
Yoon et al. teach charging and discharging of the inductor (see Fig.1 and paragraph 0008, 0024, 0026-0027, 0063, 0112, claim 1).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Yoon et al. to Hrinya et al. where storing energy or dissipating energy to inductor as taught by Hrinya et al. would be called as charging / discharging of inductor as taught by Yoon et al. in order to effectively control output voltage and to improve power transfer efficiency including stable mode transition (see Yoon et al., paragraph 0006).
Further reason to combine the teachings of Yoon et al. and Hrinya et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards regulating output volage.
Regarding claim 2, Hrinya et al. further teach, wherein the first switch corresponds to a High Side switch and the second switch corresponds to a Low Side switch (see Fig.1-8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, Q1 high side, Q2 low side switch).
Regarding claim 3, Hrinya et al. further teach, wherein the control circuit comprises a first comparator with hysteresis configured to compare the output voltage of the switching converter with the threshold voltage, and a second comparator configured to compare the output voltage with a target voltage, and wherein the first comparator with hysteresis is configured to generate a high output in response to the output voltage exceeding the threshold voltage, and the second comparator is configured to remain at a low output, that disables each of the first switch and the second switch (see Fig.1-8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, 104 first comparator, 106 second comparator).
Regarding claim 4, Hrinya et al. further teach, wherein the control circuit comprises a Set-Reset latch coupled with the at least one comparator, wherein the SR latch is configured to control the first switch and the second switch, and regulate the charging and discharging of the inductor (see Fig.1-8 and paragraph 0014-0021, 0024-0031, 0035-0036).
Regarding claim 5, Hrinya et al. further teach, wherein after activating the dummy load circuit, the control circuit is configured to: disable the dummy load after the output of a first comparator with hysteresis goes to zero, such that an unnecessary overshoot in the output voltage is prevented (see Fig.1-8 and paragraph 0014-0021, 0024-0031).
Regarding independent claim 10, Hrinya et al. teach an electronic system, comprising: a memory device; and a power supply having a switching converter (see Fig.1 and paragraph 0014-0021, unit 100 is converter); wherein the switching converter includes a first switch connected to an input voltage source and an inductor; a second switch connected to a ground terminal and the inductor (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, first switch Q1 connected to input voltage Vin, second switch Q2 connected to ground, L1 is inductor); and a control circuit connected to the first switch and the second switch, the control circuit configured to control the first switch and the second switch, wherein the first switch and the second switch are configured to regulate charging and discharging of the inductor, (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, (104+120+108+110) is controller, controlling Q1 and Q2 switch) and wherein the control circuit is configured to compare an output voltage of the switching converter with a threshold voltage using at least one comparator; detect an overshoot in the output voltage based on the comparison comparison (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, comparator 104 compare output voltage Vout with threshold voltage Vset); and perform at least one of disable, based on the detection of the overshoot in the output voltage, each of the first switch and the second switch to increase a slope of an inductor discharge current flowing across the inductor such that the overshoot in the output voltage is reduced; or activate a dummy load circuit connected at an output of the switching converter to reduce an overshoot in the output voltage (see Fig.1-8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, dummy load cancels output voltage overshoot, see specially paragraph 0035).
Even though Hrinya et al. teach wherein the first switch and the second switch are configured to regulate storing energy / dissipating energy of the inductor but silent exclusively charging and discharging of the inductor.
Yoon et al. teach charging and discharging of the inductor (see Fig.1 and paragraph 0008, 0024, 0026-0027, 0063, 0112, claim 1).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Yoon et al. to Hrinya et al. where storing energy or dissipating energy to inductor as taught by Hrinya et al. would be called as charging / discharging of inductor as taught by Yoon et al. in order to effectively control output voltage and to improve power transfer efficiency including stable mode transition (see Yoon et al., paragraph 0006).
Further reason to combine the teachings of Yoon et al. and Hrinya et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards regulating output volage.
Regarding claim 11, Hrinya et al. further teach, wherein the memory device includes a memory interface comprising a Random Access Memory (RAM) (see Fig.1-8 and paragraph 0014-0021, 0024-0030).
Regarding claim 12, Hrinya et al. further teach, wherein the switching converter is configured to provide a regulated output voltage to the memory device (see Fig.1-8 and paragraph 0014-0021, 0024-27).
Regarding claim 13, Hrinya et al. further teach, wherein the switching converter is a DC-DC switching converter (see Fig.1-8 and paragraph 0014-0021, 0024-0025).
Regarding claim 14, Hrinya et al. further teach, wherein the switching converter is one of a buck converter and a boost converter (see Fig.1-8 and paragraph 0039).
Regarding claim 15, Hrinya et al. further teach, wherein the switching converter is a buck-boost converter (see Fig.1-8 and paragraph 0014-0021, 0039).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hrinya et al. (US Pub # 2021/0099073).
Regarding independent claim 6, Hrinya et al. teach a method to reduce an overshoot in an output voltage during load transient in a switching converter (see Fig.1 and paragraph 0014-0021, unit 100 is converter), the method comprising: comparing an output voltage with a threshold voltage using a comparator; detecting an overshoot in the output voltage based on the comparison comparison (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, comparator 104 compare output voltage Vout with threshold voltage Vset); and performing at least one of disabling, based on the detection of the overshoot in the output voltage, each of a first switch and a second switch of the switching converter such that the overshoot in the output voltage is reduced (see Fig.1-2, 4, 8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, first switch Q1 connected to input voltage Vin, second switch Q2 connected to ground); or enabling, based on the detection of the overshoot in the output voltage, a dummy load connected at an output of the switching converter, such that an overshot in the output voltage is reduced (see Fig.1-8 and paragraph 0014-0021, 0024-0031, 0035-0037, 0039, dummy load cancels output voltage overshoot, see specially paragraph 0035).
Even though Hrinya et al. teach disabling current delivery to switch Q1 but silent exclusively about disabling each of a first switch and a second switch. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Yoon et al. to Hrinya et al. where disabling current flow to Q1 actually also disable Q2 as both are NMOS transistor in order to reduce output voltage overshoot and to improve overvoltage mitigation technique for switching converter (see paragraph 0003, last two lines).
Regarding claim 7, Hrinya et al. further teach, wherein the first switch corresponds to a High Side switch and the second switch corresponds to a Low Side switch (see Fig.1-8 and paragraph 0014-0021, 0024-0031,.
Regarding claim 8, Hrinya et al. further teach, wherein the first switch is connected to an input voltage source and an inductor, and the second switch is connected to a ground terminal and the inductor (see Fig.1-8 and paragraph 0014-0021, 0024-0027).
Regarding claim 9, Hrinya et al. further teach, wherein after enabling the dummy load, the method comprises: disabling the dummy load after the output of a first comparator with hysteresis goes to zero, such that an unnecessary overshoot in the output voltage is prevented (see Fig.1-8 and paragraph 0014-0021, 0024-0031, 0035-0036).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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