DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 11/01/2024. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-10, 12-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nguyen (OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems).
Claim 1: Nguyen discloses a system comprising: a processor (e.g. memory controller and OS-level Memory Fault Management module) configured to:
receive an encoded signal (e.g. Byte-Error Flag BF as defined in Equation 1, in page 7, section 4.2.1) indicating a type of an error detected (e.g. single-bit, multi-bit, parity) in a memory (e.g. DRAM with on-die ECC); and
output one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. For instance, the processor outputs mitigation commands (e.g., trigger scrubbing, update parity, retire page) based on this signal (see, e.g., Sections 4.2.1, 5.2.2, Algorithms 2 & 3, and FIG. 2-4).
As per claim 20, the claimed features are rejected similarly to claim 1 above.
Claim 2: Nguyen discloses the system of claim 1, wherein the processor is further configured to decode the encoded signal to determine the type of the error detected in the memory. For instance, Nguyen discloses that the processor (EDF module/OS) decodes the encoded Byte-Error Flag (BF) to determine the error type. The BF value directly corresponds to the error type (e.g., 0xFFFF for parity error, a single shifted bit for a data error) as described in Equation 1 and the associated diagnostic procedures (Section 5.2.2, Algorithm 2).
Claim 4: Nguyen discloses the system of claim 1, wherein the processor is further configured to select the one or more mitigation commands from multiple different mitigation commands based on the type of the error detected in the memory. For example, a single-bit transient error triggers a data rewrite (scrub) via Algorithm 3, while a permanent error triggers page retirement (Section 5.2.3). Different commands are selected for parity errors versus data errors (Algorithm 2).
Claim 5: Nguyen discloses the system of claim 1, wherein the processor is further configured to output a first set of mitigation commands if the type of the error detected in the memory corresponds to a first error type and output a second set of mitigation commands if the type of the error detected in the memory corresponds to a second error type. For instance, Nguyen explicitly discloses outputting a first set of commands (scrubbing/write-back) for transient errors (first type) and a second set of commands (page remapping) for permanent errors (second type), as outlined in the Memory Fault Management (MFM) operations (Sections 5.2.2, 5.2.3, and Table 4).
Claim 6: Nguyen discloses the system of claim 1, wherein the encoded signal comprises an alert signal. For instance, Nguyen explicitly uses the ALERT_n pin, defined in the JEDEC standard as an alert signal, to communicate the Byte-Error Flag from the DRAM to the memory controller (Sections 2.3, 4.2.1, 4.2.2, and FIG. 3). The encoded signal is this alert signal.
Claim 7: Nguyen discloses the system of claim 1, further comprising a memory system that includes at least the memory. For instance, Nguyen describes a full memory system including the memory (DRAM chips with on-die ECC) and the processor (memory controller/OS) that constitutes the claimed system (FIG. 2, System Overview).
Claim 8: Nguyen discloses the system of claim 7, wherein the memory system further includes a buffer, and wherein the processor receives the encoded signal indicating the type of error detected in the memory from the buffer. For instance, the Error Diagnostic and Fixing (EDF) module located in the memory controller contains a "catch-up error buffer" (64-byte SRAM) that stores error information before the OS processes it. The processor (OS) receives the error information (encoded signal) from this buffer (Section 5.1, FIG. 4).
Claim 9: Nguyen discloses the system of claim 1, wherein the processor receives the encoded signal indicating the type of the error detected in the memory directly from the memory. For instance, Nguyen discloses the processor (memory controller) receiving the encoded signal (Byte-Error Flag) directly from the memory via the ALERT_n pin, without an intermediary buffer for the initial signal transmission (FIG. 3, Section 4.2.2: "the 16-bit BF is transmitted to the corresponding DRAM controller through the ALERT_n pin").
Claim 10: Nguyen discloses a memory system comprising:
a memory (e.g. DRAM array; Abstract);
and a buffer (e.g. the EDF module's catch-up error buffer- page 9, section 5.1), the buffer configured to output an encoded signal (error information/BF) indicating a type of an error detected in the memory (Sections 5.1, 5.2.1, Algorithm 1).
Claim 12: Nguyen discloses the memory system of claim 10, wherein the buffer is further configured to detect the error in the memory. For instance, Nguyen discloses that the on-die ECC detects the error (e.g. section 3.3, page 5), and this information is passed to and managed by the EDF module/buffer. The buffer is part of the system configured to handle the detected error (Section 5.1, Algorithm 1 procedure EDF_INFORM_ERROR_TO_OS_MFM).
Claim 13: Nguyen discloses the memory system of claim 10, wherein the buffer is further configured to output the encoded signal indicating the type of the error detected in the memory to a processor. For instance, Nguyen's EDF module/buffer outputs the error information (encoded signal) to the OS (the processor) via an interrupt and function call, as detailed in Algorithm 1 (Sections 5.1, 5.2.1).
Claim 14: Nguyen discloses the memory system of claim 10, wherein the encoded signal comprises an alert signal (e.g. As with claim 6, the encoded signal output by Nguyen's system is carried via the ALERT_n pin, which is an alert signal (Sections 2.3, 4.2.1).
Claim 15: Nguyen discloses the memory system of claim 14, wherein the buffer is further configured to encode the alert signal with the type of the error detected in the memory. For instance, Nguyen's system encodes the error type into the Byte-Error Flag (BF) register. This encoded BF is then transmitted via the ALERT_n pin. Therefore, the buffer/EDF system outputs an alert signal encoded with the error type (Equation 1, Section 4.2.1).
Claim 20: Nguyen discloses a method comprising: detecting an error in a memory (e.g. Nguyen discloses that the on-die ECC detects the error- see section 3.3, page 5); outputting an encoded signal indicating a type of the error detected in the memory (e.g. Nguyen's EDF module/buffer outputs the error information (encoded signal) to the OS (the processor) via an interrupt and function call, as detailed in Algorithm 1 (Sections 5.1, 5.2.1)); receiving, by a processor, the encoded signal (e.g. Byte-Error Flag BF as defined in Equation 1, in page 7, section 4.2.1) indicating the type of the error (e.g. single-bit, multi-bit, parity) detected in the memory; and outputting, by the processor, one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. For instance, the processor outputs mitigation commands (e.g., trigger scrubbing, update parity, retire page) based on this signal (see, e.g., Sections 4.2.1, 5.2.2, Algorithms 2 & 3, and FIG. 2-4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen as applied to claim1 above, and further in view of Konireddygari et al (US 8,250,273 B2).
Claim 3: Nguyen teaches the system of claim 1, but fails to teach that the encoded signal is encrypted, and wherein the processor is further configured to decrypt the encoded signal to determine the type of the error detected in the memory. However, Konireddygari is directly concerned with securing interrupt signaling in a computer system. It teaches encrypting an interrupt vector (a type of encoded signal indicating an interrupt request) using a key (e.g. Abstract). It also teaches providing the key to a processor’s local interrupt controller to enable it to decrypt the encrypted interrupt vector (e.g. Abstract). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to apply the security teaching of Konireddygari to the error reporting system of Nguyen in order to prevent unauthorize access to the system.
As per claims 18 and 19, the combination of Nguyen and Konireddygari et al teach encrypting/decrypting the encoded signal, as shown in the rejection of claim 3 above.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen as applied to claim 10 above.
Claim 11: Nguyen teaches the memory system of claim 10, but fails to teach that the buffer comprises a registered clock driver. However, Nguyen teaches, in section 5.1, a buffer in the memory controller (EDF). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement such a buffer using standard memory system components, including a Registered Clock Driver (RCD), which is a common element in DIMM design for buffering addresses, commands, and clocks, to perform the stated function.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen as applied to claim 10 above, and further in view of Bains et al (US 2013/0117641 A1).
Claim 16: Nguyen teaches the memory system of claim 10, but fails to teach that the encoded signal is encoded using time domain based encoding. However, Bains teaches using an ALERT_n signal’s pulse width to differentiate between a CRC error and a Command/Address Parity error (e.g. see Figs. 4-6 & [0065]). It also describes a system where the memory controller determines the error type by decoding the duration (pulse width) of the ALERT_n signal (e.g. [0068]). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to a time-domain encoding, as taught by Bains, to implement error-type signaling system described in Nguyen in order to optimize the system.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen as applied to claim 10 above, and further in view of Crayford (US 6,078,627).
Claim 17: Nguyen teaches the memory system of claim 10, but fails to teach that the encoded signal is encoded using voltage level based encoding. However, such a technique was known in the art, before the effective filing date of the claimed invention, as disclosed by Crayford (e.g. col. 1, lines 15-24; it details the MLT-3 encoding scheme, where a +V, 0V, or -V level represents different states of the transmitted data, col. 6, lines 10-25). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to improve the teaching of Nguyen with the one taught by Crayford in order to optimize the system.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 1/22/2026