DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 11/01/2024. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Eugenio (US 10496309 B2) and further in view of Xilinx UltraScale Architecture GTY Transceivers User Guide (UG578) (Xilinx).
Claim 1: Eugenio teaches a logic die comprising:
a test circuit configured to generate test data for a feedback test operation performed on the logic die (e.g., Eugenio teaches a memory controller or host controller, item 110 in Fig. 1 or item 1228 in Fig. 12, that generates test data/training sequences for I/O testing and bit error rate (BER) analysis); and
an interface circuit connected between the test circuit (e.g., Eugenio teaches an I/O circuit (210, 310, 410, 420, 142) connected between the test logic and the external interface), the interface circuit including a write path (e.g., the path from the host to the memory device, the TX path in the transceiver), a read path (e.g., the path from the memory device back to the host, the RX path in the loopback), and a input/output circuit (e.g., the driver/receiver block, element 220, 420, 1242, that is connected to an external data signal line, e.g., a DQ pad or ball), wherein the logic die is configured such that, in a first test mode of the logic die, the test data is fed back to the test circuit via the write path and the read path and not via the TSV input/output circuit (e.g., Eugenio's "near-end PCS loopback" or "near-end PMA loopback" (element 78, paths 1 & 2) feeds test data back to the test circuit via the transmitter (write path) and receiver (read path) without going through the external I/O pads. This corresponds to "not via the TSV input/output circuit."), and wherein the logic die is configured such that, in a second test mode of the logic die, the test data is fed back to the test circuit via the write path, the input/output circuit, and the read path (e.g., Eugenio's "far-end PMA loopback" or "far-end PCS loopback" (element 78, paths 3 & 4) feeds test data back via the transmitter (write path), out through the external I/O pads (element MGTYTXP/N), and back in through the I/O pads to the receiver (read path). This corresponds to testing via the I/O circuit and the external interconnect).
Not explicitly taught by Eugenio is a "plurality of through silicon vias (TSVs) configured to communicate with a memory die.”
However, Xilinx explicitly teaches built-in self-test (BIST) features, test pattern generators, and techniques for testing through-silicon vias (TSVs) in stacked integrated circuits (e.g., pages 9, 24, 78, 143 and 219). Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify the loopback circuit of Eugenio to include and specifically test the TSV interface as taught by Xilinx, in order to ensure the integrity of the physical interconnects in a 3D stacked memory/logic configuration.
As per claim 16, the claim is parallel to claim 1 and is rejected on the same grounds. The combination of Eugenio and Xilinx renders it obvious for Eugenio's logic die (with its loopback circuit) to be stacked with memory dies via TSVs, as taught by Xilinx, to form a semiconductor device like an HBM stack.
As per claim 20, this claim recites a method corresponding to the apparatus of claim 1. Eugenio teaches the steps of transmitting test data, generating feedback in a first mode, testing the internal paths, generating feedback in a second mode, and testing the external paths. Applying this method to test the specific external path of a TSV, as taught by Xilinx, would have been obvious to a POSITA for the reasons provided in the rejection of claim 1.
Claim 2: Eugenio and Xilinx teach the logic die of claim 1, wherein the interface circuit further comprises: a selector comprising a first input terminal connected to the write path and a second input terminal connected to the TSV input/output circuit, wherein, in the first test mode, the logic die is configured such that the test data is fed back to the test circuit via the write path, the selector, and the read path, and wherein, in the second test mode, the logic die is configured such that the test data is fed back to the test circuit via the write path, the TSV input/output circuit, the TSV, the selector, and the read path. For instance, Eugenio explicitly teaches a selector/multiplexer (mux 228, 230, 424, 440) with a first input connected to an internal feedback path (e.g., from the DFE or internal write path) and a second input connected to an external feedback path (LBDQ_i). This mux selects the source for the loopback data sent back to the test circuit via the read path. Therefore, The combination of Eugenio and Xilinx renders this claim obvious for the same reasons as claim 1, with the mux structure being a standard design element for selecting between internal and external feedback sources.
Claim 3: Eugenio and Xilinx teach the logic die of claim 2, wherein the selector is configured to: select one of the first input terminal and the second input terminal based on a control signal; and provide a signal to the read path, the signal received via the selected one of the first and second input terminals. For instance, Eugenio teaches that the multiplexer is configured to select one of its input terminals based on a control signal (e.g., mode register settings, per 1108 in Fig. 11) and provide the signal from the selected terminal to the read path. This is the inherent function of a multiplexer as shown in all of Eugenio's loopback figures
Claim 4: Eugenio and Xilinx teach the logic die of claim 3, wherein, in the first test mode, the logic die is configured such that the selector selects the first input terminal, and provides a first signal received via the first input terminal to the read path, and wherein, through the first test mode, the write path, the selector, and the read path are tested. For instance, Eugenio teaches that in the first test mode, the selector chooses the internal path (mux selects the output from the DFE or internal path), thereby testing the write path, selector, and read path (Eugenio, Fig. 4, mux 424 selecting internal DFE slices).
Claim 5: Eugenio and Xilinx teach the logic die of claim 3, wherein, in the second test mode, the logic die is configured such that the selector selects the second input terminal, and provides a second signal received via the second input terminal to the read path, and wherein, through the second test mode, the TSV input/output circuit and the TSV are tested. For instance, Eugenio teaches that in the second test mode, the selector chooses the external path (mux selects LBDQ_i), thereby testing the external I/O path. When applied to the Xilinx TSV structure, this tests the TSV input/output circuit and the TSV itself.
Claim 6: Eugenio and Xilinx teach the logic die of claim 2, wherein the TSV input/output circuit comprises: a transmitter electrically connected between the write path and the TSV; and a receiver electrically connected between the TSV and the selector, wherein the logic die is configured such that, in the second test mode, the transmitter and the receiver are enabled, and the test data is fed back to the second input terminal of the selector via the write path, the transmitter, the TSV, and the receiver. For instance, Eugenio teaches a TSV I/O circuit (when combined with Xilinx) that comprises a transmitter (TX driver, element 156 in Fig. 3-30) and a receiver (RX AFE, element 170 in Fig. 4-2). It further teaches that in the far-end loopback mode, data is fed back via the transmitter, the external pad, and the receiver.
Claim 7: Eugenio and Xilinx teach the logic die of claim 6, but fail to teach that the logic die is configured such that, in the first test mode, the transmitter and the receiver are disabled, and the test data is fed back to the first input terminal of the selector via the write path. However, it is a basic and well-known principle of circuit design that when a functional block is not in use, it can be disabled (e.g., powered down or tristated) to save power and prevent signal contention. A POSITA, implementing the dual-mode test described by Eugenio for a TSV, would understand that to isolate the internal path, the TSV's transmitter and receiver should be disabled to prevent them from interfering with the internal loopback signal. This would have been an obvious design implementation.
Claim 8: Eugenio and Xilinx teach the logic die of claim 1, further comprising: a memory controller (e.g. Eugenio: item 1220, Fig. 12) configured to control a write operation and a read operation on the memory die.
Claim 9: Eugenio and Xilinx teach the logic die of claim 8, wherein the logic die is configured such that, in a write mode for the write operation, write data received from the memory controller is transmitted to the memory die via the write path, the TSV input/output circuit, and the TSV, and wherein the logic die is configured such that, in a read mode for the read operation, read data received from the memory die is transmitted to the memory controller via the TSV, the TSV input/output circuit, and the read path. For instance, Eugenio teaches that in normal operation, write data is sent via the write path and I/O circuit to the memory, and read data is received via the I/O circuit and read path (Fig. 1, Fig. 12).
Claim 10: Eugenio and Xilinx teach the logic die of claim 8, further comprising: a selection circuit including a third input terminal connected to the memory controller and a fourth input terminal connected to the test circuit, wherein the selection circuit is configured to in a write mode for the write operation and a read mode for the read operation, select the third input terminal and provide a third signal received to the interface circuit, the third signal received via the third input terminal, and in the first test mode and the second test mode, select the fourth input terminal and provide a fourth signal received to the interface circuit via the fourth input terminal. For instance, Eugenio teaches a selection circuit (e.g., the logic that decides between normal commands and test commands, 1104, 1106 in Fig. 11) that chooses between the memory controller's data path and the test circuit's data path. These are fundamental functions of a system-on-chip with integrated test features.
Claim 11: Eugenio and Xilinx teach the logic die of claim 1, but fail to teach that the test circuit comprises: a data pattern generator configured to generate the test data; and a comparator configured to compare the test data generated by the test circuit to the data fed back. However, Xilinx explicitly teaches the components of a sophisticated test circuit, including a data pattern generator (e.g., PRBS generator, 143 in Fig. 3-28) and a comparator (e.g., PRBS checker/error counter, 219 in Fig. 4-16). A POSITA, seeking to build a robust test circuit as contemplated by Eugenio for a high-speed interface, would look to standard BIST architectures like those detailed in Xilinx. Integrating a known pattern generator and comparator from Xilinx into Eugenio's test framework would have been a straightforward combination of known elements to achieve the predictable result of automated error checking.
Claim 12: Eugenio and Xilinx teach the logic die of claim 1, but fail to teach the test circuit is configured to: provide the test data having a ground voltage level to the write path, in order to test whether a short has occurred between the TSV and a power TSV to which a power voltage is applied; and determine, in the second test mode, that the short has occurred between the TSV and the power TSV when the data fed back to the test circuit does not match the test data generated by the test circuit. However, Xilinx teaches using loopback for fault detection, including detecting faults on interconnects. Testing for "stuck-at" faults (shorts to power or ground) or bridging faults (shorts between adjacent TSVs) is a fundamental purpose of structural test. A POSITA, configuring a loopback test for a TSV as in the combination of Eugenio and Xilinx, would recognize that by driving a specific logic value (e.g., 0 to test for a short to power) and reading it back, a mismatch would indicate a physical defect. This is a basic test principle that would be inherently understood and implemented by a POSITA as part of a comprehensive test strategy.
Claim 13: Eugenio and Xilinx teach the logic die of claim 1, but fail to teach that the test circuit is configured to: provide the test data having a power voltage level to the write path, in order to test whether a short has occurred between the TSV and a ground TSV to which a ground voltage is applied; and determine, in the second test mode, that the short has occurred between the TSV and the ground TSV when the data fed back to the test circuit does not match the test data generated by the test circuit. However, Xilinx teaches using loopback for fault detection, including detecting faults on interconnects. Testing for "stuck-at" faults (shorts to power or ground) or bridging faults (shorts between adjacent TSVs) is a fundamental purpose of structural test. A POSITA, configuring a loopback test for a TSV as in the combination of Eugenio and Xilinx, would recognize that by driving a specific logic value (e.g., 0 to test for a short to power) and reading it back, a mismatch would indicate a physical defect. This is a basic test principle that would be inherently understood and implemented by a POSITA as part of a comprehensive test strategy.
Claim 14: Eugenio and Xilinx teach the logic die of claim 1, wherein the test circuit is configured to: provide the test data to the write path to test whether a short circuit has occurred between the TSV and another TSV adjacent thereto,; and determine, in the second test mode, that the short circuit has occurred between the TSV and the another TSV adjacent thereto when the data fed back to the test circuit does not match the test data generated by the test circuit. However, Xilinx teaches using loopback for fault detection, including detecting faults on interconnects. Testing for "stuck-at" faults (shorts to power or ground) or bridging faults (shorts between adjacent TSVs) is a fundamental purpose of structural test. A POSITA, configuring a loopback test for a TSV as in the combination of Eugenio and Xilinx, would recognize that by driving a specific logic value (e.g., 0 to test for a short to power) and reading it back, a mismatch would indicate a physical defect. This is a basic test principle that would be inherently understood and implemented by a POSITA as part of a comprehensive test strategy.
Claim 15: Eugenio and Xilinx teach the logic die of claim 1, further comprising: at least one of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), an accelerated processing unit (APU), an application specific integrated circuit (ASIC), or an interface logic configured to communicate with the memory die. The recitation of standard processing units (CPU, GPU, NPU, etc.) on a logic die is a statement of the intended environment. The combination of Eugenio and Xilinx would inherently be implemented in a logic die that could contain such processors. It does not add a patentable distinction to the claimed test circuit and method.
As per claims 17 and 18, these claims depend from claim 16 and add limitations mirroring claims 6 and 7. They are rejected on the same grounds as claims 6, 7, and 16, based on the combination of Eugenio and Xilinx and the obvious design choice to enable/disable the transmitter/receiver for different test modes.
Claim 19: Eugenio and Xilinx teach the semiconductor device of claim 16, wherein the semiconductor device is implemented as a high bandwidth memory (HBM). For instance, Xilinx explicitly teaches that the described test techniques, including loopback and TSV testing, are applicable to High Bandwidth Memory (HBM) . Implementing the Eugenio loopback circuit in a logic die that is part of an HBM stack is the exact combination proposed and would have been obvious.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 3/3/2026